datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

IDT5V9888 View Datasheet(PDF) - Integrated Device Technology

Part NameIDT5V9888 IDT
Integrated Device Technology IDT
IDT5V9888 Datasheet PDF : 37 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
To determine if the loop is stable, the phase margin (ωm) would need to be calculated as follows.
Phase Margin:
ωz = 1 / (Rz * Cz)
ωp = Cz + Cp
Rz * Cz * Cp
(Eq. 23)
(Eq. 24)
φm = (360 / 2π ) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)]
(Eq. 25)
To ensure stability in the loop, the phase margin is recommended to be > 60° but too high will result in the lock time being excessively long. Certain loop filter
parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain loop stability.
Fc = 150KHz is the desired loop bandwidth. The total M value is 850. The ratio of ωp/ωc should be at least 4. A rule of thumb that will help to aid the way,
the ωp / ωc ratio should be at least 4. Given Fc and M, an optimal loop filter setting needs to be solved for that will meet both the PLL loop bandwidth and maintain
loop stability.
The charge pump gain should be relatively small as possible to achieve a low loop bandwidth.
Ip = 40uA .
Kφ * KVCO = 950MHz/V * 40uA = 38000A/Vs
Loop Bandwidths
ωc = 2π * Fc = 9.42x105 s-1
ωuz = ωp / ωc = 4
(Eq. 26)
ωc2 = ωp * ωz
(Eq. 27)
ωp = Cz + Cp = ωz (1 + Cz / Cp)
Rz * Cz * Cp
Solving for Cz, Cp, and Rz
Knowing ωc = Rz * Kφ * KVCO * Cz and substituting in the equations from above,
M * (Cz + Cp)
Cz >>> Cp, therefore, we can easily derive Cp to be
Cp = Kφ * KVCO = 12.60pF
M * ωc2 * ωuz
Similarly for Cz and Rz
Cz = Kφ * KVCO * (ωuz2 - 1) = Cp * (ωuz2 - 1) = 189pF
M * ωc2 * ωuz
Rz = M * ωc * ωuz2 = 22.48KΩ
Kφ * KVCO * (ωuz2 - 1)
Based on the loop filter parameter equations from above, since there are no possible values of 12.60pF for Cp, 189pF for Cz, and 22.48KΩ for Rz, the next
possible values within the loop filter settings are 12.55pF (CP[3:0]=1111), 196.4pF (CZ[3:0]=0111), and 15.3KΩ (RZ[3:0]=1111), respectively. This loop filter
setting will yield a loop bandwidth of about 102KHz. The phase margin must be checked for loop stability.
φm = (360 / 2π ) * [tan-1 (6.41x105 s-1 / 3.33x105 s-1) - tan-1 (6.41x105 s-1 / 5.54x106 s-1)] = 56°
Although slightly below 60°, the phase margin would be acceptable with a fairly stable loop.
Direct download click here

The IDT5V9888 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be pro grammed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each outputs slew rate and enable/disable function can be programmed.

• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges:
   − LVTTL: up to 200MHz
   − LVPECL/ LVDS: up to 500MHz
• Reference Crystal Input with programmable oscillator gain and
   programmable linear load capacitance
   − Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation capability
• I/O Standards:
   − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
   − Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages

Share Link : IDT
@ 2014 - 2018  [ Home ] [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]