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IDT5V9888 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR IDT
Integrated Device Technology IDT
IDT5V9888 Datasheet PDF : 37 Pages
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IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
LOOP FILTER
The loop filter for each PLL can be programmed to optimize the jitter performance. The low-pass frequency response of the PLL is the mechanism that dictates
the jitter transfer characteristics. The loop bandwidth can be extracted from the jitter transfer. A narrow loop bandwidth is good for jitter attenuation while a wide
loop bandwidth is best for low jitter generation. The specific loop filter components that can be programmed are the resistor via the RZ[3:0] bits, pole capacitor
via the CZ[3:0] bits, zero capacitor via the CP[3:0] bits, and the charge pump current via the IP[2:0] bits.
The following equations govern how the loop filter is set.
VDD
Ip
UP
From PFD
DOWN
Ip
To VCO
Rz
Cp
Cz
Charge Pump and Loop Filter Configuration
Resistor (Rz) = 0.3KΩ + RZ[3:0] * 1KΩ
(Eq. 15)
Zero capacitor (Cz) = 6pF + CZ[3:0] * 27.2pF (Eq. 16)
Pole capacitor (Cp) = 1.3pF + CP[3:0] * 0.75pF (Eq. 17)
Charge pump current (Ip) = 5 * 2IP[2:0] μA
(Eq. 18)
Parameter
Bits
Step
Min
RZ
4
1
0.3
CZ
4
27.2
6
CP
4
0.75
1.3
IP
3
2n
5
Max
Units
15.3
KΩ
414
pF
12.55
pF
640
μA
PLL loop filter design is beyond the scope of this datasheet. Refer to design procedures for 3-order charge-pump based PLLs. For the sake of simplicity,
the fastest and easiest way to calculate the PLL loop bandwidth (Fc) given the programmable loop filter parameters is as follows.
PLL Loop Bandwidth:
Charge pump gain (Kφ) = Ip / 2π (Eq. 19)
VCO gain (KVCO) = 950MHz/V * 2π (Eq. 20)
M = Total multiplier value (See the PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail)
ωc = Rz * Kφ * KVCO * Cz (Eq. 21)
M * (Cz + Cp)
Fc = ωc / 2π
(Eq. 22)
Note, the phase/frequency detector frequency (FPFD) is typically seven times the PLL closed-loop bandwidth (Fc) but too high of a ratio will reduce your
phase margin thus compromising loop stability.
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