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TAS5704 20-W Stereo Digital Audio Power Amplifier With Feedback TI
Texas Instruments TI
TAS5704 Datasheet PDF : 34 Pages
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TAS5704
SLOS563 – MARCH 2008
www.ti.com
DISSIPATION RATINGS
PACKAGE (1)
64-Pin HTQFP
TA 25°C
POWER RATING
5W
DERATING FACTOR
40 mW/°C(2)
TA = 70°C
POWER RATING
3.2 W
TA = 85°C
POWER RATING
2.6 W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the
HTQFP thermal pad.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VIH
VIL
TA
TJ
RL (BTL)
RL (SE)
RL (PBTL)
LO (BTL)
LO (SE)
LO (PBTL)
Digital/analog supply voltage
Half-bridge supply voltage
High-level input voltage
Low-level input voltage
Operating ambient temperature range
Operating junction temperature range
Load impedance
Output-filter inductance
DVDD
PVCC_xx
3.3-V TTL, 5-V tolerant
3.3-V TTL, 5-V tolerant
Output filter: L = 22 µH, C = 680 nF.
Minimum output inductance under
short-circuit condition
MIN NOM MAX
3 3.3 3.6
10
26
2
0.8
0
85
0
150
6.0
8
3.2
4
3.2
4
10
10
10
UNIT
V
V
V
V
°C
°C
µH
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER
Output sample rate 2×–1×
oversampled
TEST CONDITIONS
32–kHz data rate ±2%
44.1-, 88.2-, 176.4-kHz data rate ±2%
48-, 96-, 192-kHz data rate ±2%
MODE
12× sample rate
8×, 4×, and 2× sample rates
8×, 4×, and 2× sample rates
VALUE
384
352.8
384
UNITS
kHz
kHz
kHz
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
fMCLKI
PARAMETER
Frequency, MCLK (1 / tcyc2)
MCLK duty cycle
MCLK minimum high time
MCLK minimum low time
LRCLK allowable drift before LRCLK reset
External PLL filter capacitor C1
External PLL filter capacitor C2
External PLL filter resistor R
TEST CONDITIONS
2-V MCLK = 49.152 MHz, within the
min and max duty cycle constraints
0.8-V MCLK = 49.152 MHz, within the
min and max duty cycle constraints
SMD 0603 Y5V
SMD 0603 Y5V
SMD 0603, metal film
MIN
4.9
40%
8
TYP
50%
8
47
4.7
470
MAX
49.2
60%
UNIT
MHz
ns
ns
4 MCLKs
nF
nF
8
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