SLOS563 – MARCH 2008
CLOSED-LOOP POWER STAGE CHARACTERISTICS
The TAS5704 is PWM input power stage with a closed loop architecture. A feedback loop varies the PWM output
duty cycle with changes in the supply voltage. This ensures that the output voltage (and output power) remain
the same over transitions in the power supply.
Open-loop power stages have an output duty cycle that is equal to the input duty cycle. Since the duty cycle
does NOT change to compensate for changes in the supply voltage, the output voltage (and power) change with
supply voltage changes. This is undesirable effect that closed-loop architecture of the TAS5704 solves.
The single-ended (SE) gain of the TAS5704 is fixed, and specified below:
TAS5704 Gain = 0.13 / Modulation Level (Vrms/%)
Modulation level = fraction of full-scale modulation of the PWM signal at the input of the power stage.
TAS5704 (SE) Voltage Level (in Vrms) = 0.13 x Modulation Level
The bridge-tied (BTL) gain of the TAS5704 is equal to 2x the SE gain:
TAS5704 (BTL) Voltage Level (in Vrms) = 0.26 x Modulation Level
For a digital modulator like the TAS5704, the default maximum modulation limit is 97.7%. For a full scale input,
the PWM output switches between 2.3% and 97.7%. This equates to a modulation level of 95.4% for a full scale
input (0 dBFS).
For example, calculate the output voltage in RMS volts given a –20 dBFS signal to a digital modulator with a
maximum modulation limit of 97.7% in a BTL output configuration:
TAS5704 Output Voltage = 0.1 (–20dB) x 0.26 (Gain) x 95.4 (Modulation Level)
= 2.48 Vrms
For shutdown and power-down, the PDN terminal should be cycled low for the “turn-off” time specified in the DC
Electrical Characteristics table before PVCC falls below 10 V and DVDD/AVDD falls below 3 V. For SE mode,
this is approximately 500ms. For BTL mode, the time is much faster, at 30ms. This ensures the best “pop”
performance in the system.
To allow simplified system design, the TAS5704 requires only a single supply (PVCC) for the the power blocks
and a 3.3 V (DVDD/AVDD) supply for PWM input blocks. In addition, the high-side gate drive is provided by
built-in bootstrap circuits requiring only an external capacitor for each half-bridge.
DVDD/AVDD must be applied at the same time or before PVCC is applied on power-up. For power-down, PVCC
and DVDD/AVDD should remain active while the PDN terminal is cycled low and held low for at least the time
specified for tOFF in the Electrical Characteristics table.
In order for the bootstrap circuit to function properly, it is necessary to connect a small ceramic capacitor from
each bootstrap pin (BS_) to the corresponding output pin (OUT_). When the power-stage output is low, the
bootstrap capacitor is charged through an internal diode. When the power-stage output is high, the bootstrap
capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the
high-side gate drive.
DEVICE PROTECTION SYSTEM
The TAS5704 contains a complete set of protection circuits carefully designed to make system design efficient as
well as to protect the device against any kind of permanent failures due to short circuits, overtemperature,
overvoltage, and undervoltage.
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