|TAS5704||20-W Stereo Digital Audio Power Amplifier With Feedback|
|TAS5704 Datasheet PDF : 34 Pages |
SLOS563 – MARCH 2008
The digital portion of the chip requires 3.3 V, and the power section operates from a variable range from 10 V to
Clock, Auto Detection, and PLL
The TAS5704 DAP is a clock slave device. It accepts MCLK, SCLK, and LRCLK.
The TAS5704 checks to verify that SCLK is a specific value of 32-fs, 48- fs, or 64-fs. The DAP only supports a 1 ×
fs LRCLK. The timing relationship of these clocks to SDIN1 and SDIN2 is shown in subsequent sections. The
clock section uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce the
The DAP can auto-detect and set the internal clock control logic to the appropriate settings for the frequencies of
32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed (176.4 kHz or 192
The DAP (digital audio processor) has four channels of high-performance digital PWM modulators that are
designed to drive bridge-tied output H-bridge configurations with AD or BD modulation and single-ended output
configurations with AD modulation.
The DAP uses noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and
high-performance digital audio reproduction.
The PWM section accepts 24-bit PCM data from the DAP and outputs up to 4 PWM audio output channels.
The PWM section has individual channel dc blocking filters that are ALWAYS enabled. The filter cutoff frequency
is less than 1 Hz.
SERIAL DATA INTERFACE
Serial data is input on SDIN1 and SDIN2. The PWM outputs are derived from SDIN1 and SDIN2. The TAS5704
DAP accepts 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 18-, 20-, or 24-bit data in
left-justified, right-justified, and I2S serial data formats. See Table 1 for format control settings.
SERIAL INTERFACE CONTROL AND TIMING
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A system clock (SCLK) running at
32, 48, or 64 × fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal
changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge
of the bit clock. The DAP masks unused trailing data bit positions.
(= 32 fS, 48 fS or 64 fS)
N−1 N−2 N−3
N–1 N–2 N–3
Figure 26. I2S Format
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5704
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