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FX805LG View Datasheet(PDF) - CML Microsystems Plc

Part Name
Description
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FX805LG
CML
CML Microsystems Plc CML
FX805LG Datasheet PDF : 17 Pages
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Controlling Protocol ......
“Read NRZ Rx Data Register” – A/C 74 (7C ), followed by 1 byte of Reply Data.
H
H
Received NRZ data bits are organized into bytes and
made available to the µController via the Reply Data line. As
8 bits are received into this register an interrupt is generated
to indicate that a complete byte has been received, this byte
must be read before the arrival of the last (8th) bit of the next
incoming byte, if this is not done, an interrupt to indicate this
condition will be generated and the previous Rx data is
discarded (See Table 4, Status Register, Bits 2 and 3).
Word synchronization is not provided. Byte
synchronization and any codeword recognition will be
performed by the host µController. The Rx baud rate is set
by writing to the CTCSS Tx Frequency/NRZ Baud Rate
Register (73 /7B ). The first bit received is the first bit sent to
H
H
the µController.
This register is not affected by the General Reset
command (01 ) and may adopt any random configuration at
H
Power-Up.
“Write to NRZ Tx Data Register” – A/C 75 (7D ), followed by 1 byte of Command Data.
H
H
A byte for transmission is loaded from the “C-BUS”
Command Data line with this A/C. The first data-bit received
via the “C-BUS” is transmitted first. This transmitter
operation is non-inverting.
The first data-byte loaded after the NRZ Encoder is
enabled (Control Register) initiates the transmission
sequence and an interrupt will be generated when the NRZ
Tx Data Buffer is ready for the next data-byte.
Subsequently, interrupts occur for every 8 bits transmitted.
Transmission is terminated, the Tx Sub-Audio Output placed
at V , and an interrupt generated if the next byte is not
BIAS
loaded within 7 bit periods. (See Table 4, Status Register,
Bits 4 and 5).
This register is not affected by the General Reset
command (01 ) and may adopt any random configuration at
H
Power-Up.
“Write to Gain-Set Register” – A/C 76H (7EH), followed by 1 byte of Command Data.
Setting
MSB
76 5 4
00 0 0
Gain Setting
Transmitted Bit 7 First
These 4 Bits Must be “0”
3
Pre-Emphasis Setting
1
1.72dB Gain Enabled
0
1.72dB Gain Disabled
2
1
0
Tx Level Adjust Gain Setting
0
0
0
-2.58
dB
0
0
1
-1.72
dB
0
1
0
-0.86
dB
0
1
1
0
dB
1
0
0
+0.86
dB
1
0
1
+1.72
dB
1
1
0
+2.58
dB
1
1
1
Not Used
Table 7 Gain-Set Register Settings
The Gain-Set Register Settings
The settings of this register control the CTCSS and NRZ
signal level that is presented at the Tx Sub-Audio Output.
Bit 3, when enabled, is used to produce a pre-emphasis
effect on the NRZ Tx Data by increasing the gain of the data
bit before a level change (Figure 8 below), by 1.72dB to
make that data pulse level slightly more positive (or
negative). The signal level will be 1.72dB greater than that
set by Bits 0 to 2. If the Tx Sub-Audio Output level is set to
+2.58dB, the pre-emphasized level will be +4.3dB.
The pre-emphasis function, will remain enabled until
disabled by setting Bit 3 to a logic “0.” If this function remains
enabled when using the CTCSS Encoder the output signal
level may be adversely affected, therefore this function
should only be enabled when in the NRZ Encode mode.
This register is not affected by the General Reset
command (01 ) and may adopt any random configuration at
H
Power-Up.
NRZ Tx DATA
BIT PERIODS
GAIN-SET NRZ Tx DATA with PRE-EMPHASIS ENABLED
Gain-Set
+1.72dB
Gain-Set
+1.72dB
Fig.8 Gain-Set with Pre-Emphasis
12
Gain-Set
+1.72dB
Gain-Set
+1.72dB
 

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