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M5-128/104-10HC View Datasheet(PDF) - Lattice Semiconductor

Part Name
Description
View to exact match
M5-128/104-10HC
Lattice
Lattice Semiconductor Lattice
M5-128/104-10HC Datasheet PDF : 47 Pages
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Clock Line 1 Options
x Global clock (0, 1, 2, or 3) with positive edge clock enable
x Global clock (0, 1, 2, or 3) with negative edge clock enable
x Global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase)
Clock Line 2 Options
x Global clock (0, 1, 2, or 3) with clock enable
Clock Line 3 Options
x Complement of clock line 2 (same clock enable)
x Product-term clock (if clock line 2 does not use clock enable
PT (0:3)
PINCLK (0:3)
MUX 4TO1
0 IN (0)
1 IN (1)
2 IN (2) OUT
3 IN (3)
PT0
U1
F0 F1
MUX 4TO1
0
1
2
3
IN (0)
IN (1)
IN (2) OUT
IN (3)
PT1
U2
F0 F1
PT2
CLKIN
Clock Enable
MUX 2TO1
N (0)
OUT
N (1)
F0
MUX 2TO1
/CLK
CLK0
F0
/CLK
CLK
OUT
CLKEN1
BIPHASE
CLKEN2
CLK1
PT (0:2)
PT0
PT1
SET0/RST0
MUX 2TO1
PT1
OUT
/PT1(ST)
F0
SET1/RST1
MUX 4TO1
0
1
2
3
IN (0)
IN (1)
IN (2) OUT
IN (3)
U3
F0 F1
PT3
MUX
2TO1
CLKIN
Clock Enable
CLK2
MUX 2TO1
/CLK2
PTCLK
F0
CLK3
20446G-004
Figure 4. Clock Generator
Block
Clocks
0–3
MUX 2TO1
PT2
PT2
SET2/RST2/LE
OUT
/PT2
F0
Block
Sets/Reset
02, LE
20446G-005
Figure 5. Set/Reset Generator
The set/reset generation portion of the control generator (Figure 5) creates three set/reset lines for
the PAL block. Each macrocell can choose one of these three lines or choose no set/reset at all.
All three lines can be configured for product term set/reset and two of the three lines can be
configured as sum term set/reset and one of the lines can be configured as product-term or sum-
term latch enable. While the set/reset signals are generated in the control generator, whether that
signal sets or resets a flip-flop is determined within the individual macrocell. The same signal can
set one flip-flop and reset another. PT2 or /PT2 can also be used as a latch enable for macrocells
configured as latches.
MACH 5 Family
7
 

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