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M5-128/104-10VI View Datasheet(PDF) - Lattice Semiconductor

Part Name
Description
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M5-128/104-10VI
Lattice
Lattice Semiconductor Lattice
M5-128/104-10VI Datasheet PDF : 47 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Device
M5-1282
M5-128/1
M5LV-128
M5-192/1
M5-2562
M5-256/1
M5LV-256
M5-320
M5LV-320
M5-384
M5LV-384
M5-512
M5LV-512
Table 2. MACH 5 Speed Grades
Speed Grade1
-5
-6
-7
-10
-12
-15
-20
C
C, I
C, I
C, I
I
C
C, I
C, I
C, I
C, I
I
C
C,I
C, I
C, I
I
C
C, I
C, I
C, I
C, I
I
C
C, I
C, I
C, I
I
C
C, I
C, I
C, I
C, I
I
C
C, I
C, I
C, I
I
C
C, I
C, I
C, I
C, I
I
C
C, I
C, I
C, I
C, I
I
C3
C, I3
C, I
C, I
C, I
I
C3
C, I3
C, I
C, I
C, I
I
C3
C, I3
C, I
C, I
C, I
I
C3
C, I3
C, I
C, I
C, I
I
Note:
1. C = Commercial grade, I = Industrial grade
2. /1 version recommended for new designs
3. Preliminary specificatons
With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512
macrocells to support full system logic integration. Extensive routing resources ensure pinout
retention as well as high utilization. It is ideal for PAL® block device integration and a wide range
of other applications including high-speed computing, low-power applications, communications,
and embedded control. At each macrocell density point, Lattice offers several I/O and package
options to meet a wide range of design needs (Table 3).
Supply Voltage
100-pin TQFP
100-pin PQFP
144-pin TQFP
144-pin PQFP
160-pin PQFP
208-pin PQFP
240-pin PQFP
256-ball BGA
352-ball BGA
Table 3. MACH 5 Package and I/O Options 1
M5-128/1
M5LV-128
M5-192/1
M5-256/1
M5LV-256
M5-320
M5LV-320
M5-384
M5LV-384
5
3.3
5
5
3.3
5
3.3
5
3.3
68
68, 74
68
68 68*, 74
68
68*
68*
68*
68
104
104
104
104* 104* 104* 104*
120
120
120
120
120
120*
120
120*
120
160
160
160
160
160
160
184* 184* 184* 184*
192
192* 192* 192*
Note:
1. The I/O options indicated with a “*” are obsolete, please contact factory for more information.
M5-512
M5LV-512
5
3.3
120*
120
160
160
184* 184*
192* 192*
256
256
MACH 5 Family
3
 

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