M5-128/104-10HC View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
View to exact match
M5-128/104-10HC Datasheet PDF : 47 Pages
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Feature
Supply Voltage (V)
Macrocells
Maximum User I/O Pins
tPD (ns)
tSS (ns)
tCOS (ns)
fCNT (MHz)
Typical Static Power (mA)
IEEE 1149.1 Boundary Scan Compliant
PCI-Compliant
Table 1. MACH 5 Device Features 1
M5-128/1
M5LV-128
M5-192/1
M5-256/1
M5LV-256
M5-320
M5LV-320
5
3.3
5
5
3.3
5
3.3
128 128
192
256 256 320 320
120 120
120
160 160 192 192
5.5 5.5
5.5
5.5
5.5
6.52 6.52
3.0 3.0
3.0
3.0
3.0
3.02 3.02
4.5 4.5
4.5
4.5
4.5
5.02 5.02
182 182
182
182 182 1672 1672
35
35
45
55
55
70
70
Yes Yes
Yes
Yes Yes Yes Yes
Yes Yes
Yes
Yes Yes Yes Yes
M5-384
M5LV-384
5
3.3
384 384
160 192
6.52 6.52
3.02 3.02
5.02 5.02
1672 1672
75
75
Yes Yes
Yes Yes
Note:
1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.
2. Preliminary specifications for new 6.5ns (Tpd) speed grade. 7.5ns speed grade in production now.
M5-512
M5LV-512
5
3.3
512 512
256 256
6.52 6.52
3.02 3.02
5.02 5.02
1672 1672
100 100
Yes Yes
Yes Yes
GENERAL DESCRIPTION
The MACH® 5 family consists of a broad range of high-density and high-I/O Complex
Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds
at high CPLD densities, low power, and supports additional features such as in-system
programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH
5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation.
Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process
technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The
5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification.
2
MACH 5 Family
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