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GMT
Global Mixed-mode Technology Inc
Description : Dual Bidirectional I2C Bus and SMBus Voltage-Level Translator

General Description
The G3401 is a dual bidirectional I2C and SMBUS voltage-level Translator with an enable (EN) input, and is operational from 1.2V to 3.3V VREF1 and 2.5V to 5.5V VREF2 . It allows bidirectional voltage translations between 1.2V and 5V, without use of directional pin. The low ON-state resistance (rON) of the switch ensures the connections to be with minimal propagation delay. When EN is high, the Translator switch is ON, and the SCL1 I/O and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the Translator switch is off, and a high-impedance exists between ports.

Features
■ 2-Bit Bidirectional Translator for SDA and SCL Lines in Mix-Mode I2C Applications
■ I2C and SMBus Compatible
■ Less than 1.5ns Maximum Propagation Delay to Accommodate Standard-Mode and Fast-Model I2C Devices and Multiple Masters
■ Allows Voltage-Level Translator Between
    ♦ 1.2V VREF1 and 2.5V, 3.3V, 5V VREF2
    ♦ 1.8V VREF1 and 3.3V, 5V VREF2
    ♦ 3.3V VREF1 and 5V VREF2
■ Provides Bidirectional Voltage Translation without Direction Pin
■ Low 3.5Ω ON-State Connection Between Input and Output Ports Provides Less Signal Distortion
■ Open-Drain I2C I/O Ports
■ 5V Tolerant I2C I/O Ports to Support Mixed Mode Signal Operation
■ High Impedance SCL1,SDA1,SCL2 and SDA2 Pins for EN=Low
■ Lock-up-Free Operation for Isolation When EN=Low

Part Name(s) : G3403 G3403TL1U
GMT
Global Mixed-mode Technology Inc
Description : Bidirectional I2C Bus and SMBus Voltage Level Translator

General Description
The G3403 is a bidirectional I2C and SMBUS voltage-level Translator with an enable (EN) input, and is operational from 1.2V to 3.3V VREF1 and 2.5V to 5.5V VREF2 . It allows bidirectional voltage translations between 1.2V and 5V, without use of directional pin. The low ON-state resistance (rON) of the switch ensures the connections to be with minimal propagation delay. When EN is high, the Translator switch is ON, and the SCL1 I/O is connected to the SCL2 I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the Translator switch is off, and a high-impedance exists between ports.

Features
■ 1-Bit Bidirectional Translator
■ I2C and SMBus Compatible
■ Less than 1.5ns Maximum Propagation Delay to Accommodate Standard-Mode and Fast-Model I2C Devices and Multiple Masters
■ Allows Voltage-Level Translator Between
    ♦ 1.2V VREF1 and 2.5V, 3.3V, 5V VREF2
    ♦ 1.8V VREF1 and 3.3V, 5V VREF2
    ♦ 3.3V VREF1 and 5V VREF2
■ Provides Bidirectional Voltage Translation without Direction Pin
■ Low 3.5Ω ON-State Connection Between Input and Output Ports Provides Less Signal Distortion
■ Open-Drain I2C I/O Ports
■ 5V Tolerant I2C I/O Ports to Support Mixed Mode Signal Operation
■ High Impedance for SCL1 and SCL2 as EN=Low
■ Lock-up-Free Operation for Isolation When EN=Low

Description : Frequency Synthesizer

DESCRIPTION
The M2004-01 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Translator in a 9mm x 9mm surface mount package.
The internal high “Q” SAW filter provides low jitter signal performance and determines the maximum output Frequency of the VCSO. A programmable output divider can divide the VCSO Frequency to achieve an output as low as 38.88MHz.
The input to the Frequency Translator is provided by selecting between one of two output reference clocks. The output Frequency is an integer multiple of the input reference Frequency.
Parallel and serial control of the output and feedback dividers is provided via the configuration logic. An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock.
The M2004-01 is available at SONET/SDH and 10GbE frequencies up to 700MHz.

FEATURES
■ Output Clock Frequency up to 700MHz
■ Differential LVPECL Outputs
■ Internal Low-jitter SAW-based Oscillator
■ Intrinsic Jitter <1ps rms (12kHz - 20MHz)
■ Jitter Attenuation of Input Reference Clock
■ Dual Input MUX
■ Parallel Programming
■ Tunable Loop Filter Response
■ Differential LVPECL Outputs
■ 3.3V Operation
■ Small 9mm x 9mm SMT Package

APPLICATIONS
■ SONET / SDH / 10GbE System Synchronization
■ Add / Drop Muxes, Access and Edge Switches
■ Line Card System Clock Cleaner / Translator
■ Optical Module Clock Cleaner / Translator

 

Description : Low Power Single Supply Hex TTL-to-PECL Translator

General Description
The 100391 is a hex Translator for converting TTL logic levels to F100K PECL logic levels. The unique feature of this Translator, is the ability to do this translation using only one +5V supply. The differential outputs allow each circuit to be used as an inverting/non-inverting Translator, or as a differential line driver. A common enable (E), when LOW, holds all inverting outputs HIGH and all non-inverting inputs LOW.
The 100391 is ideal for those mixed PECL/TTL applications which only have +5V supply available. When used in the differential mode, the 100391, due to its high common mode rejection, overcomes voltage gradients between the TTL and PECL ground systems.

Features
■ Operates from a single +5V supply
■ Differential PECL outputs
■ 2000V ESD protection
■ Companion chip to 100390 hex PECL-to-TTL Translator

Description : MICROSTEPPING DMOS DRIVER WITH Translator

MICROSTEPPING DMOS DRIVER WITH Translator

The A3977xED and A3977xLP are complete microstepping motor drivers with built-in Translator. They are designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 35 V and ±2.5 A. The A3977 includes a fixed off-time current regulator that has the ability to operate in slow-, fast-, or mixed-decay modes. This currentdecay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation.
The Translator is the key to the easy implementation of the A3977. By simply inputting one pulse on the STEP input the motor will take one step (full, half, quarter, or eighth depending on two logic inputs). There are no phase-sequence tables, high-Frequency control lines, or complex interfaces to program. The A3977 interface is an ideal fit for applications where a complex µP is unavailable or over-burdened.

FEATURES
■ ±2.5 A, 35 V Output Rating
■ Low rDS(on) Outputs, 0.45 Ω Source, 0.36 Ω Sink Typical
■ Automatic Current Decay Mode Detection/Selection
■ 3.0 V to 5.5 V Logic Supply Voltage Range
■ Mixed, Fast, and Slow Current Decay Modes
■ Home Output
■ Synchronous Rectification for Low Power Dissipation
■ Internal UVLO and Thermal Shutdown Circuitry
■ Crossover-Current Protection

ON-Semiconductor
ON Semiconductor
Description : Quad MECL to TTL Translator

Quad MECL to TTL Translator

The MC10125 is a quad Translator for interfacing data and control signals between the MECL section and saturated logic sections of digital systems. The MC10125 incorporates differential inputs and Schottky TTL “totem pole” outputs. Differential inputs allow for use as an inverting/ non–inverting Translator or as a differential line receiver. The VBBreference voltage is available on pin 1 for use in single–ended input biasing. The outputs of the MC10125 go to a low logic level whenever the inputs are left floating.

 

Motorola
Motorola => Freescale
Description : 9−Bit ECL/TTL Translator

9−Bit ECL/TTL Translator

The MC10H/100H601 is a 9–bit, dual supply ECL to TTL Translator. Devices in the Motorola 9–bit Translator series utilize the 28–lead PLCC for optimal power pinning, signal flow–through and electrical performance.
The devices feature a 48 mA TTL output stage, and AC performance is specified into both a 50 pF and 200 pF load capacitance. For the 3–state output disable, both ECL and TTL control inputs are provided, allowing maximum design flexibility.
The 10H version is compatible with MECL 10H ECL logic levels. The 100H version is compatible with 100K levels.

• 9–Bit Ideal for Byte–Parity Applications
• 3–State TTL Outputs
• Flow–Through Configuration
• Extra TTL and ECL Power Pins to Minimize Switching Noise
• ECL and TTL 3–State Control Inputs
• Dual Supply
• 4.8 ns Max Delay into 50 pF, 9.6 ns into 200 pF (all outputs switching)
• PNP TTL Inputs for Low Loading

Motorola
Motorola => Freescale
Description : 9-Bit Latch ECL/TTL Translator

9-Bit Latch ECL/TTL Translator

The MC10H/100H603 is a 9–bit, dual supply ECL to TTL Translator.
Devices in the Motorola 9–bit Translator series utilize the 28–lead PLCC for optimal power pinning, signal flow–through and electrical performance.
The devices feature a 48 mA TTL output stage, and AC performance is specified into both a 50 pF and 200 pF load capacitance. Latching is controlled by Latch Enable (LEN), and Master Reset (MR) resets the latches. A HIGH on OEECL sends the outputs into the high impedance state. All control inputs are ECL level.
The 10H version is compatible with MECL 10H ECL logic levels. The 100H version is compatible with 100K levels.

• 9–Bit Ideal for Byte–Parity Applications
• 3–State TTL Outputs
• Flow–Through Configuration
• Extra TTL and ECL Power Pins to Minimize Switching Noise
• Dual Supply
• 6.0 ns Max Delay into 50 pF, 12 ns into 200 pF (all outputs switching)
• PNP TTL Inputs for Low Loading

Description : LOW-POWER HEX TTL-TO-PECL Translator

DESCRIPTION
The SY100S391 is a hex TTL-to-PECL Translator for converting TTL logic levels to 100K logic levels. The unique feature of this Translator is the ability to do this translation using only one +5V supply. The differential outputs allow each circuit to be used as an inverting/non-inverting Translator, or as a differential line driver. A common enable (E), when LOW, holds all inverting outputs HIGH and all non-inverting inputs LOW.

FEATURES
■ Operates from a single +5V supply
■ Differential PECL outputs
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC packages

Motorola
Motorola => Freescale
Description : Quad CMOS to PECL* Translator

Quad CMOS to PECL* Translator

The MC10H352 is a quad Translator for interfacing data between a CMOS logic section and the PECL section of digital systems when only a +5.0 Vdc power supply is available. The MC10H352 has CMOS compatible inputs and PECL complementary open–emitter outputs that allow use as an inverting/non–inverting Translator or as a differential line driver. When the common strobe input is at a low logic level, it forces all true outputs to the PECL low logic state (≈ +3.2 V) and all inverting outputs to the PECL high logic state (≈ +4.1 V).
The MC10H352 can also be used with the MC10H350 to transmit and receive CMOS information differentially via balanced twisted pair lines.

• Single +5.0 V Power Supply
• All VCC Pins Isolated On Chip
• Differentially Drive Balanced Lines
• tpd = 1.3 nsec Typical

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