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ADF4106BCP View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADF4106BCP
ADI
Analog Devices ADI
ADF4106BCP Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
Table III. Reference Counter Latch Map
ADF4106
RESERVED
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
0
0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)
X = DONT CARE
R14
R13
R12
..........
R3
R2
R1
DIVIDE RATIO
0
0
0
..........
0
0
1
1
0
0
0
..........
0
1
0
2
0
0
0
..........
0
1
1
3
0
0
0
..........
1
0
0
4
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
1
1
1
..........
1
0
0
16380
1
1
1
..........
1
0
1
16381
1
1
1
..........
1
1
0
16382
1
1
1
..........
1
1
1
16383
ABP2
0
0
1
1
ABP1
0
1
0
1
ANTIBACKLASH PULSEWIDTH
2.9ns
1.3ns
6.0ns
2.9ns
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION
LDP
OPERATION
0
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION
REV. 0
–11–
 

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