datasheetbank_Logo
Технический паспорт Поисковая и бесплатно техническое описание Скачать

AK4527B Просмотр технического описания (PDF) - Asahi Kasei Microdevices

Номер в каталоге
Компоненты Описание
производитель
AK4527B
AKM
Asahi Kasei Microdevices AKM
AK4527B Datasheet PDF : 33 Pages
ASAHI KASEI
[AK4527B]
n Reset Function
When RSTN = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog outputs go
to VCOM voltage, DZF1-2 pins go to “H” and SDTO pin goes to “L”. Because some click noise occurs, the analog output
should muted externally if the click noise influences system application. Figure 7 shows the power-up sequence.
RSTN bit
Internal
RSTN bit
ADC Internal
State
4~5/fs (9)
1~2/fs (9)
Normal Operation
Digital Block Power-down
516/fs (1)
Init Cycle
Normal Operation
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
Normal Operation
Digital Block Power-down
GD (2)
(3)
“0”data
Normal Operation
GD
(4)
DAC In
(Digital)
“0”data
(2)
GD
GD
DAC Out
(Analog)
(6) (5)
(6)
Clock In
MCLK,LRCK,SCLK
(7)
Don’t care
45/fs (8)
DZF1/DZF2
Notes:
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
noise influences system application. Required muting time depends on the configuration of the input buffer circuits.
Figure 12,13: 1s
Figure 14,15: 200ms
(5) The analog outputs go to VCOM voltage.
(6) Click noise occurs at 45/fs after RSTN bit becomes “0”, and occurs at 12/fs after RSTN bit becomes “1”. This
noise is output even if “0” data is input.
(7) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode. When exiting the reset mode, “1”
should be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed.
(8) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 6~7/fs after RSTN bit becomes “1”.
(9) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
Figure 7. Reset sequence example
MS0056-E-00
- 21 -
2000/10
 

Share Link: