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STA015B View Datasheet(PDF) - STMicroelectronics

Part Name
Description
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STA015B Datasheet PDF : 44 Pages
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STA015-STA015B-STA015T
Figure 3. Test Circuit (refer to SO28 package)
OUT_CLK/DATA_REQ
VDD
100nF
VSS
VDD
100nF
VSS
VDD
100nF
VSS
VDD
100nF
VDD PVDD VSS
4.7µF
4.7µF
VSS PVSS
28
1
2
14
13
16
15
23
22
17
18
100nF
PVDD
PVSS
26
RESET
3
4
9
10
11
12
5
6
7
25
8
27
21
20
19
24
TESTEN
SDA
SCL
SDO
SCKT
LRCKT
OCLK
SDI
SCKR
BIT_EN
SDI_ADC
SCR_INT
LRCK_ADC
XTI
XTO
470pF
10K
1K
4.7nF
D00AU1143
PVSS
Figure 4. Test Load Circuit
VDD
IOL
Test Load
Output
SDA
Other Outputs
IOL
1mA
100µA
IOH
100µA
CL
100pF
100pF
VREF
3.6V
1.5V
OUTPUT
CL
IOH
VREF
D98AU967
2. FUNCTIONAL DESCRIPTION
2.1 - Clock Signal
The STA015 input clock is derivated from an ex-
ternal source or from a industry standard crystal
oscillator, generating input frequencies of 10,
14.31818 or 14.7456 MHz.
Other frequencies may be supported upon re-
quest to STMicroelectronics. Each frequency is
supported by downloading a specific configura-
tion file, provided by STM
XTI is an input Pad with specific levels.
Symbol
VIL
VIH
Parameter
Low Level Input Voltage
High Level Input Voltage
Test Condition
Min.
VDD-0.8
Typ.
Max.
VDD-1.8
Unit
V
V
CMOS compatibility
The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical
CMOS pads.
TTL compatibility
The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD =
3V TTL min high level = 2.0V while XTI min high level = 2.2V)
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