STA015 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
View to exact match
STA015 Datasheet PDF : 44 Pages
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STA015-STA015B-STA015T
MUTE
Address: 0x14 (20)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
XXXXXXX 0
1
X = don’t care; 0 = normal operation; 1 = mute
The MUTE command is handled according to the
state of the decoder, as described in section 2.5.
MUTE sets the clock running.
DATA_REQ_ENABLE
Address: 0x18 (24)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
b2
X
X
X
X
X
0
X
X
X
X
X
1
The DATA_REQ_ENABLE register is used to
configure Pin n. 28 working as buffered output
clock or data request signal, used for multimedia
CMD_INTERRUPT
Address: 0x16 (22)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
X
X
X
X
X
X
X
0
1
X = don’t care;
0 = normal operation;
1 = write into I2C/Ancillary Data
The INTERRUPT is used to give STA015 the
command to write into the I2C/Ancillary Data
Buffer (Registers: 0x7E ... 0xB5). Every time the
Master has to extract the new buffer content it
writes into this register, setting it to a non-zero
value.
LSB
b1
b0
X
X
X
X
Description
buffered output clock
request signal
mode.
The buffered Output Clock has the same fre-
quency than the input clock (XTI)
SYNCSTATUS
Address: 0x40 (64)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
SS1
SS0
0
0
0
1
1
0
Description
Research of sync word
Wait for Confirmation
Synchronised
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