STA013T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
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STA013T Datasheet PDF : 38 Pages
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STA013 - STA013B - STA013T
PLLFRAC_441_H
Address: 0x52
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8
The registers are considered logically concate-
nated and contain the fractional values for the
PLL, for 44.1KHz reference frequency.
(see also PLLFRAC_L and PLLFRAC_H regis-
ters)
PCMDIVIDER
Address: 0x54
Type: RW
Software Reset: 0x03
Hardware Reset: 0x03
7
6
5
4
3
2
1
0
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PCMDIVIDER is used to set the frequency ratio
between the OCLK (Oversampling Clock for
DACs), and the SCKT (Serial Audio Transmitter
Clock).
The relation is the following:
SCKT_freq
=
2
OCLK_freq
(1 + PCM_DIV)
The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression:
1) OCLK_freq = O_FAC * LRCKT_ Freq
(DAC relation)
2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32*
LRCKT_Freq (when 16 bit PCM mode is used)
3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64*
LRCKT_Freq (when 32 bit PCM mode is used)
4) PCM_DIV = (O_FAC/64) - 1 in 16 bit mode
5) PCM_DIV = (O_FAC/128) - 1 in 32 bit mode
Example for setting:
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
0
0
0
0
0
1
1
1
16 bit mode
512 x Fs
0
0
0
0
0
1
0
1
16 bit mode
384 x Fs
0
0
0
0
0
0
1
1
16 bit mode
256 x Fs
0
0
0
0
0
0
1
1
32 bit mode
512 x Fs
0
0
0
0
0
0
1
0
32 bit mode
384 x Fs
0
0
0
0
0
0
0
1
32 bit mode
256 x Fs
for 16 bit PCM Mode
O_FAC = 512 ; PCM_DIV = 7
O_FAC = 256 ; PCM_DIV = 3
O_FAC = 384 ; PCM_DIV = 5
for 32 bit PCM Mode
O_FAC = 512 ; PCM_DIV = 3
O_FAC = 256 ; PCM_DIV = 1
O_FAC = 384 ; PCM_DIV = 2
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