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AD9048KQ View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
AD9048KQ
ADI
Analog Devices ADI
AD9048KQ Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Figure 3. Dynamic Performance (20 MHz Encode Rate)
AD9048
Ceramic 0.1 µF decoupling capacitors should be placed as closely
as possible to the supply pins of the AD9048. For decoupling
low frequency signals, use 10 µF tantalum capacitors, also con-
nected as closely as practical to voltage supply pins.
Within the AD9048, reference currents may vary because of
coupling between the clock and input signals. As a result, it is
important that the ends of the reference ladder, RT (Pin 18) and
RB (Pin 28), be connected to low impedances (as measured
from ground).
If the AD9048 is being used in a circuit in which the reference
is not varied, a bypass capacitor to ground is strongly recom-
mended. In applications that use varying references, they must
be driven from a low impedance source.
Figure 4. Dynamic Performance (35 MHz Encode Rate)
LAYOUT SUGGESTIONS
Designs that use the AD9048 or any other high speed device
must follow some basic layout rules to ensure optimum
performance.
The first requirement is to have a large, low impedance ground
plane under and around the converter. If the system uses sepa-
rate analog and digital grounds, both should be solidly con-
nected together, and to the ground plane, as closely to the
AD9048 as practical to avoid ground loop currents.
Figure 5. Typical Connections
REV. C
–7–
 

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