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AD9048SQ View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD9048SQ Monolithic 8-Bit Video A/D Converter ADI
Analog Devices ADI
AD9048SQ Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
AD9048
THEORY OF OPERATION
Refer to the Functional Block Diagram of the AD9048. The
AD9048 comprises three functional sections: a comparator
array, encoding logic and output latches.
Within the array, the analog input signal to be digitized is com-
pared with 255 reference voltages. The outputs of all compara-
tors whose references are below the input signal level will be
high; outputs whose references are above that level will be low.
The n-of-255 code that results from this comparison is applied
to the encoding logic where it is converted into binary coding.
When it is inverted with dc signals applied to the NLINV and/or
NMINV pins, it becomes twos complement.
After encoding, the signal is applied to the output latch circuits
where it is held constant between updates controlled by the
application of CONVERT pulses.
The AD9048 uses strobed latching comparators in which com-
parator outputs are either high or low, as dictated by the analog
input level. Data appearing at the output pins have a pipeline
delay of one encode cycle.
Input signal levels between the references applied to RT (Pin 18)
and RB (Pin 26) will appear at the output as binary numbers
between 0 and 255, inclusive. Signals outside that range will
show up as either full-scale positive or full-scale negative out-
puts. No damage will occur to the AD9048 as long as the input
is within the voltage range of VEE to +0.5 V.
The significantly reduced input capacitance of the AD9048
lowers the drive requirements of the input buffer/amplifier and
also induces much smaller phase shift in the analog input signal.
Applications that depend on controlled phase shift at the con-
verter input can benefit from using the AD9048 because of its
inherently lower phase shift.
The CONVERT, analog input and digital output circuits are
shown in Figure 1.
System timing, which provides details on delays through the
AD9048 as well as the relationships of various timing events, is
shown in Figure 2.
Dynamic performance of the AD9048, i.e., typical signal-to-
noise ratio, is illustrated in Figures 3 and 4.
Figure 1. Input/Output Circuits
Figure 2. Timing Diagram
–6–
REV. C
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