ADM1232AARN View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
ADM1232AARN Datasheet PDF : 6 Pages
| |||
ADM1232A–SPECIFICATIONS (VCC = Full Operating Range, TA = TMIN to TMAX unless otherwise noted)
Parameter
Min
Typ
Max
Units Test Conditions/Comments
TEMPERATURE
POWER SUPPLY
Voltage
Current
STROBE AND PB RESET INPUTS
Input High Level
Input Low Level
INPUT LEAKAGE CURRENT
(STROBE, TOLERANCE)
TD
OUTPUT CURRENT
RESET
RESET, RESET
OUTPUT VOLTAGE
RESET/RESET
RESET/RESET High Level
RESET/RESET Low Level
–40
+85
°C
TA = TMIN to TMAX
4.5
5.0
5.5
V
20
50
µA
VIL, VIH = CMOS Levels
200
500
µA
VIL, VIH = TTL Levels
2.0
VCC + 0.3 V
–0.3
+0.8
V
–1.0
1.6
+1.0
µA
µA
8
10
–8
–12
mA When VCC Is at 4.5 V–5.5 V
mA When VCC Is at 4.5 V–5.5 V
VCC – 0.5 VCC – 0.1
0.4
2.4
V
While sourcing less than 500 µA, RESET remains
within 0.5 V of VCC on power-down until VCC
drops below 2.0 V. While sinking less than
500 µA, RESET remains within 0.5 V of GND
on power-down until VCC drops below 2.0 V.
V
V
1 V OPERATION
RESET Output Voltage
RESET Output Voltage
VCC – 0.1
0.1
V
While Sourcing Less than 50 µA
V
While Sinking Less than 50 µA
VCC TRIP POINT
5%
10%
CAPACITANCE
Input (STROBE, TOLERANCE)
Output (RESET, RESET)
PB RESET
Time
Delay
4.5
4.62
4.74
V
TOLERANCE = GND
4.25
4.37
4.49
V
TOLERANCE = VCC
20
1
4
5
pF TA = +25°C
7
pF TA = +25°C
ms PB RESET Must Be Held Low for a Minimum
20
ms of 20 ms to Guarantee a Reset
RESET ACTIVE TIME
STROBE
Pulsewidth
Timeout Period
VCC
Fall Time
Rise Time
250
610
1000
ms
20
ns
62.5
150
250
ms TD = 0 V
250
600
1000
ms TD = Floating
500
1200
2000
ms
TD = VCC
10
µS
Guaranteed by Design
0
µS
Guaranteed by Design
VCC FAIL DETECT TO RESET OUTPUT DELAY
RESET AND RESET Are Logically Correct
250
610
50
1000
µs
After VCC Falls Below the Set Tolerance Voltage
(Figure 5)
ms After VCC Rises Above the Set Tolerance Voltage
Specifications subject to change without notice.
–2–
REV. 0
|
|
Share Link: 