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PM8313 View Datasheet(PDF) - PMC-Sierra

Part Name
Description
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PM8313
PMC-Sierra
PMC-Sierra PMC-Sierra
PM8313 Datasheet PDF : 192 Pages
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DATA SHEET
PMC-920702
ISSUE 5
PM8313 D3MX
M13 MULTIPLEXER
off-line framer, indicating both OOF and COFA events. Even if an OOF is
indicated, the framer will continue indicating performance monitoring information
based on the previous frame alignment.
Status signals such as the RED alarm, alarm indication signal, and the idle
signal are detected. The framer employs a simple integration algorithm (with a
1:1 slope) that is based on the occurrence of "valid" M-frame intervals. For the
RED alarm, an M-frame is said to be a "valid" interval if it contains a RED defect,
defined as an occurrence of an OOF or LOS event during that M-frame. For AIS
and IDLE, an M-frame is said to be a "valid" interval if it contains AIS or idle,
defined as the occurrence of less than 15 discrepancies in the expected signal
pattern ("1010" or "1111" for AIS; "1100" for idle) while valid frame alignment is
maintained. The discrepancy threshold ensures the detection algorithms operate
in the presence of bit error rates of up to 10-3. For AIS, the expected pattern
may be selected to be: the framed "1010" signal; the framed arbitrary DS3 signal
and the C-bits all zero; the framed "1010" signal and the C-bits all zero; the
framed all-ones signal (with overhead bits ignored); or the unframed all-ones
signal (with overhead bits equal to ones). Each "valid" M-frame interval causes
an associated integration counter to increment; "non-valid" M-frames cause a
decrement. With the slow detection option, RED, AIS, or idle is declared if the
associated count saturates at 127 which results in a detection time of 13.5 ms.
With the fast detection option, RED, AIS, or idle is declared if the associated
count saturates at 21 which results in a detection time of 2.23 ms. RED, AIS, or
idle declaration is deasserted when the associated interval count decrements
to 0.
Valid X-bits are extracted by the FRMR to provide indication of far end receive
failure. The FERF status is set to logic 1 if the extracted X-bits are equal and are
logic 0 (i.e. X1=X2=0); the status is set to logic 0 if the extracted X-bits are equal
and are logic 1(i.e. X1=X2=1). If the X-bits are not equal, the FERF status
remains in its previous state. The extracted FERF status is buffered for 2 M-
frames before being reported within the DS3 FRMR Status register or being
output on the RFERF pin. This buffer ensures a better than 99.99% chance of
freezing the FERF status on a correct value during the occurrence of an out of
frame. When an OOF occurs, the FERF value is held at the state contained in
the buffer location corresponding to the second to last M-frame. This location is
not updated until the OOF condition is deasserted. Meanwhile, the buffer
location corresponding to the last M-frame is continually updated every M-frame
based on the above FERF definition. Once correct frame alignment has been
found and OOF is deasserted, the buffer location corresponding to the last M-
frame will contain valid FERF status and the buffer location corresponding to the
second to last M-frame is enabled to be updated every M-frame.
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