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PM8313 View Datasheet(PDF) - PMC-Sierra

Part Name
Description
View to exact match
PM8313
PMC-Sierra
PMC-Sierra PMC-Sierra
PM8313 Datasheet PDF : 192 Pages
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DATA SHEET
PMC-920702
ISSUE 5
PM8313 D3MX
M13 MULTIPLEXER
7 PIN DESCRIPTION
Pin Name
RCLK/
VCLK
RPOS/
RDAT
RNEG/
RLCV
ROCLK
Type Pin No. Function
Input
Input
26 The receive input clock (RCLK) provides timing
for the receive side of the D3MX. RCLK is
nominally a 44.736 MHz, 50% duty cycle clock.
The test vector clock (VCLK) signal is used
during D3MX production testing to verify
internal functionality.
29 The positive input pulse (RPOS) signal
represents the positive pulses received on the
B3ZS-encoded line when configured for dual
rail reception. The receive data input (RDAT)
signal represents the unipolar DS3 input
stream when configured for single rail
operation. Both RPOS and RDAT are sampled
on the rising edge of RCLK by default and may
be enabled to be sampled on the falling edge of
RCLK.
Input
30 The negative input pulse (RNEG) signal
represents the negative pulses received on the
B3ZS-encoded line when configured for dual
rail reception. Line code violations (LCVs) may
be input on the receive line code violation
(RLCV) signal when configured for single rail
operation. Both RNEG and RLCV are sampled
on the rising edge of RCLK by default and may
be enabled to be sampled on the falling edge of
RCLK.
Output
10 The receive output clock (ROCLK) signal
provides timing for downstream processing.
ROCLK is nominally a 44.736 MHz, 50% duty
cycle clock. RODAT, RMFP, RMSFP, RLOS,
REXZ and ROHP are updated on the falling
edge of ROCLK. ROCLK is a buffered version
of RCLK.
14
 

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