DATA SHEET
PMC-920702
ISSUE 5
PM8313 D3MX
M13 MULTIPLEXER
parity mode operation, up to 16,383 C-bit parity error events per second, and
16,383 far end block error (FEBE) events per second.
• Detects and validates bit-oriented codes in the C-bit parity far end alarm and
control channel.
• Terminates the C-bit parity path maintenance data link with an integral HDLC
receiver having a 4-byte deep FIFO buffer. Supports polled, interrupt-driven
or DMA access.
• Optionally extracts the C-bit parity mode path maintenance data link signal
and serializes it at 28.2 kbit/s.
• Extracts the X, P, M, F, C and stuff opportunity bits and serializes them at
526 kbit/s on a time division multiplex signal.
Each DS3 transmit framer section:
• Provides the overhead bit insertion for a DS3 stream.
• Provides a bit serial clock and data interface, and allows the M-frame
boundary and/or the overhead bit positions to be located via an external
interface
• Provides optional insertion of the X, P, M, F, C, and stuff opportunity bits via a
526 kbit/s serial interface.
• Provides B3ZS encoding.
• Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS)
and the idle signal when enabled by external inputs, or internal register bits.
• Provides diagnostic features to allow the generation of line code violation
error events, parity error events, framing bit error events, and when enabled
for the C-bit parity application, C-bit parity error events, and far end block
error events.
• Inserts bit-oriented codes in the C-bit parity far end alarm and control
channel.
• Optionally inserts the C-bit parity path maintenance data link with an integral
HDLC transmitter. Supports polled, interrupt-driven, or DMA access.
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