PM8313 View Datasheet(PDF) - PMC-Sierra

Part Name

Description

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PM8313

M13 MULTIPLEXER

PMC-Sierra 

DATA SHEET

PMC-920702

ISSUE 5

PM8313 D3MX

M13 MULTIPLEXER

1 FEATURES

• Integrates a full featured M13 multiplexer and DS-3 framer in a single

monolithic device.

• Supports the M23 or C-bit parity DS3 formats.

• Supports the M12 or G.747 formats allowing DS1 or E1 signals to be

multiplexed into a DS3 signal.

• • Allows the M12 stages to be bypassed allowing direct input of DS2 signals

into the M23 multiplexer stage.

• Provides a generic microprocessor interface for configuration, control, and

status monitoring.

• Low power CMOS technology.

• Packaged in a 208 pin Plastic Quad Flat Pack (PQFP) package.

Each DS3 framer/performance monitor section:

• Frames to a DS3 signal with a maximum average reframe time of less than

1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191

Section 5.2).

• Decodes a B3ZS-encoded signal and indicates line code violations. The

definition of line code violation is software selectable.

• Detects and accumulates occurrences of excessive zeros and loss of signal.

• Provides indication of M-frame and M-subframe boundaries, and overhead bit

positions in the DS3 stream.

• Detects the DS3 alarm indication signal (AIS) and idle signal. Detection

algorithms operate correctly in the presence of a 10-3 bit error rate.

• Extracts valid X-bits and indicates far end receive failure. Accumulates up to

65,535 line code violation (LCV) events per second, 16,383 P-bit parity error

events per second, 1023 F-bit or M-bit (framing bit) events per second,

65,535 excessive zero (EXZ) events per second, and when enabled for C-bit

1

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