LC72342G/W View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
View to exact match
LC72342G/W
SANYO -> Panasonic
LC72342G/W Datasheet PDF : 12 Pages
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Continued from preceding page.
Pin No.
Pin
I/O
LC72341G/W, 72342G/W, 72343G/W
Function
FM VCO (local oscillator) input.
This pin is selected with the PLL instruction CW1.
56
FMIN
I
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
I/O circuit
CMOS amplifier input
AM VCO (local oscillator) input.
This pin and the bandwidth are selected with the PLL instruction CW1.
CW1 b1, b0
Bandwidth
57
AMIN
I
1 0 2 to 40 MHz (SW)
1 1 0.5 to 10 MHz (MW, LW)
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
CMOS amplifier input
Push-pull CMOS
The main charge pump output. When the local oscillator frequency divided by N is higher output
than the reference frequency a high level is output, when lower, a low level is output, and
59
E0
O the pin is set to the high-impedance state when the frequencies match.
Output goes to the high-impedance state in backup mode, in halt mode, after a reset, and
in PLL stop mode.
60
AIN
Transistor used for the low-pass filter amplifier.
61
AOUT
O
Connect AGND to ground.
62
AGND
24
VSS
— Power supply pin. This pin must be connected to ground.
58
VSS
— Power supply pin. This pin must be connected to ground.
55
VDD
— Power supply pin. This pin must be connected to VDD.
Handling of Unused Pins
Pin No. Pin
3 to 6 PA port
7 to 10 PB port
11 to 14 PC port
15 to 18 PD port
19, 20 PE port
21 to 23 PF port
25 to 28 PG/S ports
29 to 32 PH/S ports
33 to 41 S port
45 to 48 COM
49
DBR1
50
DBR2
51
DBR3
52
DBR4
53
RES
54
HCTR
56
FMIN
57
AMIN
59
EO
60
AIN
61
AOUT
63
TEST1
2
TEST2
I/O type
I
O
I/O
I/O
O
I
I/O/S
I/O/S
O
O
—
—
—
—
I
I
I
I
O
I
O
I
I
Pin handling
Connect to VDD or VSS. May be left open if the pull-up resistor is selected with the IOS instruction.
Open
Connect to VDD or VSS when input is selected. Leave open if output is selected.
Connect to VDD or VSS when input is selected. Leave open if output is selected.
Open
Connect to VDD or VSS. The PF2 pin only may be left open if the pull-up resistor is selected with the IOS instruction.
Connect to VDD or VSS when input is selected. Leave open if output or LCD operation is selected.
Connect to VDD or VSS when input is selected. Leave open if output or LCD operation is selected.
Open
Open
Connect to DBR2 through a capacitor.
Connect to DBR1 through a capacitor.
Connect to VSS through a capacitor.
Connect to VSS through a capacitor.
VDD
VSS Leave open if FMIN is used.
VSS
VSS
Open
VSS
Open
Connect to VSS or leave open. Connection to VSS is preferable.
Connect to VSS or leave open. Connection to VSS is preferable.
No. 5799-9/12
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