LC72343W View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
View to exact match
LC72343W
SANYO -> Panasonic
LC72343W Datasheet PDF : 12 Pages
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LC72341G/W, 72342G/W, 72343G/W
Continued from preceding page.
Pin No.
Pin
25
PG3/S20
26
PG2/S19
27
PG1/S18
28
PG0/S17
29
PH3/S16
30
PH2/S15
31
PH1/S14
32
PH0/S13
I/O
Function
LCD driver segment output and general-purpose I/O shared function ports. The IOS
instruction is used for switching both between the segment output and general-purpose
I/O functions and between input and output for the general-purpose I/O port function.*
• When used as segment output ports
The general-purpose I/O port function is selected with the IOS instruction (Pwn = 8).
b0 = S17 to 20/PG0 to 3 (0: Segment output, 1: PG0 to 3)
The general-purpose I/O port function is selected with the IOS instruction (Pwn = 9).
b0 = S13 to 16/PH0 to 3 (0: Segment output, 1: PH0 to 3)
• When used as general-purpose I/O ports
I/O The IOS instruction (Pwn = 6,7) is used to select input or output. Note that the mode can
be set in a bit unit.
b0 = PG0
b0 = PH0
b1 = PG1
[0: Input, 1: Output]
b2 = PG2
b1 = PH1
[0: Input, 1: Output]
b2 = PH2
b3 = PG3
b3 = PH3
In backup mode, these pins go to the input disabled, high-impedance state if set up as
general-purpose outputs, and are fixed at the low level if set up as segment outputs.
These ports are set up as segment outputs after a reset.
Although the general-purpose port/LCD port setting is a mask option, the IOS instruction
must be used as described above to set up the port function.
I/O circuit
CMOS push-pull circuit
S16 to
S1
33 to 44
LCD driver segment output pins.
A 1/4-duty 1/2-bias drive technique is used.
O The frame frequency is 75 Hz.
In backup mode, the outputs are fixed at the low level.
After a reset, the outputs are fixed at the low level.
CMOS push-pull circuit
COM4
45
COM3
46
COM2
47
COM1
48
LCD driver common output pins.
A 1/4-duty 1/2-bias drive technique is used.
O The frame frequency is 75 Hz.
In backup mode, the outputs are fixed at the low level.
After a reset, the outputs are fixed at the low level.
DBR4
49
DBR3
50
DBR2
51
DBR1
52
LCD power supply stepped-up voltage pins.
System reset input.
53
RES
I In CPU operating mode or halt mode, applications must apply a low level for at least one
full machine cycle to reset the system and restart execution with the PC set to location 0.
This pin is connected in parallel with the internal power on reset circuit.
Universal counter dedicated input port.
• When taking frequency measurements, select the HCTR frequency measurement mode
and measurement time with the UCS instruction (b3 = 0, b2 = 0) and start the count with
a UCCinstruction.
CMOS input/analog
input
UCS b3, b2 Input pin Measurement mode
UCS b1, b0 Measurement time
70
HCTR
I
0 0 HCTR Frequency measurement
01 —
00
1 ms
01
4 ms
10 —
10
8 ms
11 —
11
32 ms
The CNTEND flag is set when the count completes. Since this circuit functions as an AC
amplifier, always use capacitor coupling with the input signal. Input is disabled in backup
mode, in halt mode, after a reset, and in PLL stop mode.
Note: * Applications must establish the output data in advance with an OUT, SPB, or RPB instruction and then set the pin to output mode with an IOS
instruction when using the I/O switchable ports as output pins.
Continued on next page.
No. 5799-8/12
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