LC72343W View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
View to exact match
LC72343W
SANYO -> Panasonic
LC72343W Datasheet PDF : 12 Pages
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Pin Functions
Pin No.
Pin
64
XIN
1
XOUT
63
TEST1
2
TEST2
6
PA0
5
PA1
4
PA2
3
PA3
LC72341G/W, 72342G/W, 72343G/W
I/O
Function
I
Connections for a 75-kHz crystal oscillator element
O
I/O circuit
I
IC test pins. These pins must be tied to ground.
I
Input with built-in pull-
down resistor
Special-purpose key return signal input ports designed with a low threshold voltage.
When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key
I presses can be detected. The four pull-down resistors are selected together in a single
operation using the IOS instruction (PWn = 2, b1); they cannot be specified individually.
Input is disabled in backup mode, and the pull-down resistors are disabled after a reset.
Special-purpose key source signal output ports. Since unbalanced CMOS output
Unbalanced CMOS
push-pull circuit
10
PB3
transistor circuits are used, diodes to prevent short-circuits when multiple keys are
9
PB2
pressed are not required. These ports go to the output high-impedance state in backup
O mode. These ports go to the output high-impedance state after a reset and remain in that
8
PB1
state until an output instruction (OUT, SPB, or RPB) is executed.
7
PB0
Care is required in designing the output loads if these pins are used for functions other
than key source outputs.
14
PC0
13
PC1
CMOS push-pull circuit
12
PC2
General-purpose I/O ports*. PD0 can be used as an external interrupt port. Input or
11
PC3
output mode can be set in a bit unit using the IOS instruction (Pwn = 4, 5). A value of 0
I/O specifies input, and 1 specifies output. These ports go to the input disabled high-
18
INT/PD0
impedance state in backup mode. They are set to function as general-purpose input ports
17
PD1
after a reset.
16
PD2
15
PD3
20
BEEP/PE0
19
PE1
General-purpose output ports with shared beep tone output function (PE0 only). The
BEEP instruction is used to switch PE0 between the general-purpose output port and
beep tone output functions. To use PE0 as a general-purpose output port, execute a
BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output port.
The b0 and b1 bits are used to select the beep tone frequency. There are two beep tone
frequencies supported.
When PE0 is set up as the beep tone output, executing an output instruction to PN0 only
changes the state of the internal output latch, it does not affect the beep tone output in
any way. Only the PE0 pin can be switched between the general-purpose output
function and the beep tone output function; the PE1 pin only functions as a general-
purpose output. These pins go to the high-impedance state in backup mode and remain
in that state until an output instruction or a BEEP instruction is executed. Since these
ports are open-drain ports, resistors must be inserted between these pins and VDD.
These ports are set to their general-purpose output port function after a reset.
N-channel open drain
General-purpose input and A/D converter input shared function ports (PF2 is a general-
purpose input only port). The IOS instruction (Pwn = FH) is used to switch between the
general-purpose input and A/D converter port functions. The general-purpose input and
CMOS input/analog
input
A/D converter port functions can be switched in a bit unit, with 0 specifying general-
purpose input, and 1 specifying the A/D converter input function. To select the A/D
23
PF0/ADI0
converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1.
The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is
22
PF1/ADI1
I set when the conversion completes. The INR instruction is used to read in the data.
21
PF2
If an input instruction is executed for one of these pins which is set up for analog input,
the read in data will be at the low level since CMOS input is disabled. In backup mode
these pins go to the input disabled high-impedance state. These ports are set to their
general-purpose input port function after a reset. The A/D converter is a 5-bit successive
approximation type converter, and features a conversion time of 1.28 ms. Note that the
full-scale A/D converter voltage (1FH) is (63 ยท 96)VDD.
Note: * Applications must establish the output data in advance with an OUT, SPB, or RPB instruction and then set the pin to output mode with an IOS
instruction when using the I/O switchable ports as output pins.
Continued on next page.
No. 5799-7/12
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