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OP490G View Datasheet(PDF) - Analog Devices

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OP490G Datasheet PDF : 16 Pages
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OP490
WAFER TEST LIMITS (@ VS = ؎1.5 V to ؎15 V, TA = 25؇C, unless otherwise noted)
Parameter
Symbol
Conditions
Limits
Unit
Input Offset Voltage
Input Offset Current
Input Bias Current
Large Signal Voltage Gain
Input Voltage Range
Output Voltage Swing
VOS
IOS
VCM = 0 V
IB
VCM = 0 V
AVO
VS = ± 15 V, VO = ± 10 V,
RL = 100 kW
RL = 10 kW
V+ = 5 V, V– = 0 V
1 V < VO < 4 V, RL = 100 kW
IVR
V+ = 5 V, V– = 0 V
VS = ± 15 V*
VO
VS = ± 15 V
RL = 10 kW
RL = 2 kW
VOH
V+ = 5 V, V– = 0 V, RL = 2 kW
VOL
V+ = 5 V, V– = 0 V, RL = 10 kW
0.75
5
20
500
250
125
0/4
–15/+13.5
± 13.5
± 10.5
4.0
500
mV max
nA max
nA max
V/mV min
V/mV min
V/mV min
V min
V min
V min
V min
V min
mV max
Common-Mode Rejection Ratio
CMRR
V+ = 5 V, V– = 0 V, 0 V < VCM < 4 V
80
VS = ± 15 V, –15 V < VCM < +13.5 V
90
dB min
dB min
Power Supply Rejection Ratio
PSRR
10
mV/V max
Supply Current (All Amplifiers)
ISY
VS = ± 15 V, No Load
80
mA max
NOTE
*Guaranteed by CMRR test.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
V+
+IN
OUTPUT
–IN
V–
Figure 1. Simplified Schematic
–4–
REV. C
 

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