datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

LC72349G View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
View to exact match
LC72349G Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Pin Functions
Pin No.
Pin
I/O
LC72348G/W, 72349G/W
Function
64
XIN
I
75 kHz oscillator connections
1
XOUT
O
I/O circuit
63
TEST1
2
TEST2
6
PA0
5
PA1
4
PA2
3
PA3
I
IC testing. These pins must be connected to ground during normal operation.
I
Special-purpose key return signal input ports designed with a low threshold voltage.
When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key
I
presses can be detected. The four pull-down resistors are selected together in a
single operation using the IOS instruction (PWn = 2, b1); they cannot be specified
individually. Input is disabled in backup mode, and the pull-down resistors are
disabled after a reset.
Input with built-in
pull-down resistor
General-purpose CMOS and n-channel open-drain output shared-function ports.
The IOS instruction (Pwn = 2) is used for function switching.
Unbalanced CMOS push-
pull/n-channel open-drain
10
PB0
(b0: PB0, b2: PB1, b3: PB2, PB3) (0: general-purpose CMOS, 1: n-channel open-
drain)
9
PB1
Special-purpose key source signal output ports. Since unbalanced CMOS output
8
PB2
O transistor circuits are used, diodes to prevent short-circuits when multiple keys are
pressed are not required. These ports go to the output high-impedance state in
7
PB3
backup mode. These ports go to the output high-impedance state after a reset and
remain in that state until an output instruction (OUT, SPB, or RPB) is executed.
*: Verify the output impedance conditions carefully if these pins are used for functions
other than key source outputs.
14
PC0
13
PC1
12
PC2
General-purpose I/O ports.
11
PC3
PD0 can be used as an external interrupt port. Input or output mode can be set
I/O individually using the IOS instruction by the bit (Pwn = 4, 5). A value of 0 specifies
18
INT/PD0
input, and 1 specifies output. These ports go to the input disabled high-impedance
17
PD1
16
PD2
state in backup mode. They are set to function as general-purpose input ports after a
reset.
15
PD3
*2
CMOS push-pull
20
BEEP/PE0
19
PE1
General-purpose output ports with shared beep tone output function (PE0 only). The
BEEP instruction is used to switch PE0 between the general-purpose output port and
beep tone output functions. To use PE0 as a general-purpose output port, execute a
BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output
port. The b0 and b1 bits are used to select the beep tone frequency. There are two
beep tone frequencies supported.
*: When PE0 is set up as the beep tone output, executing an output instruction to PE0
only changes the state of the internal output latch, it does not affect the beep tone
output in any way. Only the PE0 pin can be switched between the general-purpose
output function and the beep tone output function; the PE1 pin only functions as a
general-purpose output. These pins go to the high-impedance state in backup
mode and remain in that state until an output instruction or a BEEP instruction is
executed. Since these ports are open-drain ports, resistors must be inserted
between these pins and VDD. These ports are set to general-purpose output port
function after a reset.
N-channel open-drain
Continued on next page.
No. 6472-7/14
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]