LC72348 View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

View to exact match

LC72348

Low-Voltage ETR Controller with On-Chip LCD Driver

SANYO -> Panasonic 

LC72348G/W, 72349G/W

Continued from preceding page.

Instruc-

tions

Mnemonic

SS

RS

TST

TSF

TUL

PLL

UCS

UCC

BEEP

DZC

TMS

IOS

IN

OUT

INR

SPB

RPB

TPT

TPF

Operand

1st 2nd

Function

Operations function

Instruction format

f edcba9876543210

SWR N Set status register

(Status W-reg) N ← 1

1 1 1 1 1 1 1 1 0 0 0 SWR

N

SWR N Reset status register

(Status W-reg) N ← 0

1 1 1 1 1 1 1 1 0 0 1 SWR

N

SRR N Test status register true

if (Status R-reg) N = all 1 1 1 1 1 1 1 1 0 1 SRR

N

SRR N Test status register false

if (Status R-reg) N = all 1 1 1 1 1 1 1 1 1 0 SRR

N

N

Test Unlock F/F

if Unlock F/F (N) = all 0s,

then skip

000000001101

N

M

Load M to PLL register

PLL reg ← PLL data

1 1 1 1 1 0 DH

DL

r

I

Set I to UCCW1

UCCW1 ← I

000000000001

I

I

Set I to UCCW2

UCCW2 ← I

000000000010

I

I

Beep control

BEEP reg ← I

000000000110

I

I

Dead zone control

DZC reg ← I

000000001011

I

I

Set timer register

Timer reg ← I

000000001100

I

PWn N Set port control word

IOS reg PWn ← N

11111110

PWn

N

M Pn Input port data to M

M ← (Pn)

1 1 1 0 1 0 DH

DL

Pn

M Pn Output contents of M to port

P1n ← M

1 1 1 0 1 1 DH

DL

Pn

M Pn Input port data to M

M ← (Pn)

0 0 1 1 1 0 DH

DL

Pn

P1n N Set port1 bits

(Pn)N ← 1

00000010

Pn

N

P1n N Reset port1 bits

(Pn)N ← 0

00000011

Pn

N

Test port1 bits, then skip if all bits

P1n N specified are true

if (Pn)N = all 1s, then skip 1 1 1 1 1 1 0 0

Pn

N

Test port1 bits, then skip if all bits

P1n N specified are false

if (Pn)N = all 0s, then skip 1 1 1 1 1 1 0 1

Pn

N

BANK

I

Select Bank

BANK ← I

000000000111

I

LCDA

LCDB

LCPA

LCPB

HALT

CKSTP

NOP

M

I

M

I

M

I

M

I

I

Output segment pattern to LCD

digit direct

Output segment pattern to LCD

digit through LA

Halt mode control

Clock stop

No operation

LCD (DIGIT) ← M

LCD (DIGIT) ← LA ← M

HALT reg ← I,

then CPU clock stop

Stop x’tal OSC

No operation

1 1 0 0 0 0 DH

DL

1 1 0 0 0 1 DH

DL

1 1 0 0 1 0 DH

DL

1 1 0 0 1 1 DH

DL

000000000100

000000000101

000000000000

DIGIT

DIGIT

DIGIT

DIGIT

I

No. 6472-13/14

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