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MT88V32AP Просмотр технического описания (PDF) - Mitel Networks

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MT88V32AP 8 x 4 High Performance Video Switch Array Mitel
Mitel Networks Mitel
MT88V32AP Datasheet PDF : 14 Pages
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MT88V32
®
8 x 4 High Performance Video Switch Array
Preliminary Information
Features
• 32 bidirectional CMOS "T" switches in an 8×4
non-blocking array
• Break-before-make switching configuration
• Fast setup & hold times for switch programming
• 3dB bandwidth of 200MHz
• Low feedthrough and crosstalk, better than -80dB
at 5MHz
• Very low differential gain and phase errors
• 12Vpp bipolar signal capability
• On-state resistance 75(max) for VDD=+5V,
VEE=-7V
• Switch control through 2-stage latches
• Orthogonal Xi and Yi pin connections for
optimized PCB layout
• Latch readback capability for monitoring
Applications
• High-end video routing and switching
• Medical instrumentation
• Automatic test equipment (ATE)
• Multi-media communication
Description
The MT88V32 is a digitally programmable (TTL levels)
8×4 crosspoint switch that is designed to control wide-
band analog (video) signal.
ISSUE 1
August 1993
Ordering Information
MT88V32AP 44 Pin PLCC
-40° to 85°C
Each of the 32 nodes of the switching matrix has a T-
switch, see Fig.1. This grounds the nodes of all open
connections, which greatly reduces feedthrough
noise. In order to reduce crosstalk, individual analog
signal lines are isolated by interleaving them with
ground lines.
The two stage programmable latch system allows
the state of all switching nodes to be updated
simultaneously. The next state of the switch is written
into the first stage of the latches through individual
write cycles. These changes will not affect the
current state of the switch. The STROBE2 control
input is used to load the state of all first stage latches
to the second stage latches, which updates the
complete matrix. Therefore, all 32 switching nodes
are updated simultaneously.
The MT88V32 supports separate analog (VEE) and
digital (VDD) voltage references. This allows the user
to select an optimum analog signal bias point.
GND
MR
STROBE2
STROBE1
Y0-Y7
8x4
"T" Switch Array
VDD VEE VSS
2nd Stage Latches
1st Stage Latches
Address Decode
I/O
Control
Logic
X0
X1
X2
X3
R/W
DATA
CS
Yi
Xi
GND
T-Switch Configuration
AX0-AX1
AY0-AY2
Figure 1 - Functional Block Diagram
3-51
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