UTC TEA1062N / TEA1062AN
LINEAR INTEGRATED CIRCUIT
Vi
C1
100 µF
10 µF
Vi
R1 620Ω
13
10 IR VCC
7 MIC+
6 MIC-
1
LN QR 4
GAR 5
R4
100kΩ
11 DTMF
GAS1 2
12 MUTE
R7
GAS2 3 68kΩ
VEE REG AGC STAB SLPE
9
14 15
C3
4.7 µF
R6
8
R5
16
R9
3.6kΩ 20Ω
100 µF
C4
100pF
RL
600Ω
C7 1nF
Vo
C8 1nF
C6
100pF
10 TO 140 mA
Fig.13 Test circuit defining voltage gain of MIC+,MIC- and DTMF inputs.
Voltage gain is defined as : GV=20*log(|VO/Vi|).For measuring the gain from MIC+ and MIC- the MUTE input
should be HIGH(UTC TEA1062N is LOW) or open-circuit, for measuring the DTMF input MUTE should be
LOW(UTC TEA1062N is HIGH) .Inputs not under test should be open-circuit.
C1
100µF
10 µF
Vi
R1=620Ω
13
VCC
10 IR
7 MIC+
6 MIC-
11 DTMF
1
LN
4
QR
GAR 5
GAS1 2
12 MUTE
GAS2 3
VEE REG AGC STAB SLPE
9
C3
4.7 µF
14
R6
15
8
R5
16
R9
3.6kΩ 20Ω
R4
100kΩ
100 µF
C2 ZL
C4 Vo
100pF
600Ω
C7 1nF
R7
68kΩ
C8 1nF
C6
100pF
10 TO 140 mA
Fig.14 Test circuit for defining voltage gain of the receiving amplifier.
Voltage gain is defined as: GV=20*log(|VO/Vi|).
UTC
UNISONIC TECHNOLOGIES CO., LTD. 12
QW-R108-011,A