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74LVQ373MSAX View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
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74LVQ373MSAX Datasheet PDF : 6 Pages
1 2 3 4 5 6
Functional Description
The LVQ373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D-type input changes. When LE is
LOW, the latches store the information that was present on
the D-type inputs a setup time preceding the HIGH-to-LOW
Truth Table
transition of LE. The 3-STATE standard outputs are con-
trolled by the Output Enable (OE) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance mode
but this does not interfere with entering new data into the
latches.
Inputs
Outputs
LE
OE
Dn
On
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH to Low transition of Latch Enable
Logic Diagram
DS011359-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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