STW8009B27R/LF View Datasheet(PDF) - STMicroelectronics
Part Name
Description
View to exact match
STW8009B27R/LF Datasheet PDF : 66 Pages
| |||
Control registers
STw8009/STw8019
Note:
REGISTER 5
content
default
configuration5
selrst_
inc
bkdac2
bkdac1
0
0
0
Address: 0x0005
[0]
[0]
Type: R/W
[0]
[0]
dacinv
0
selrst_inc: Choice of Digital Frequency Synthesizer increment after soft reset or when
ph_rst_mode = ‘01’ . See Register 8.
(*) 0 = hard wired value (depending on TV standard)
1 = soft (value from registers 10 to 12)
bkdacN: blanking of DACs (N = 1 or 2)
(*) 0 = DAC N in normal operation
1 = DAC N input code forced to black level for C output or blanking level for Y or CVBS
output depending of dac12_conf bit of configuration13 register.
dacinv: ‘Inverts’ DAC codes to compensate for an inverting output stage in the application
(*) 0 = non inverted DAC inputs (outputs)
1 = inverted DAC inputs (outputs)
REGISTER 6
content
default
configuration6
Address: 0x0006
softreset
jump
dec_ninc
free_
jump
cfc1
0
0
0
1
0
Type: R/W
cfc0
0
[0]
maxdyn
0
softreset: software reset
(*) 0 = no reset
1 = software reset
Bit ‘softreset’ is automatically reset after internal reset generation. Software reset is active
during 4 PIX_CLK periods. When softreset is activated, all the device is reset as with
hardware reset except for the first nine user registers (registers 0 to 8:
configurations).Registers 10 up to 14 (increment and phase of oscillator), 25-30, 31-33 and
39-42 are never reset (hard/soft).
Table 10. jump, dec_ninc, free_jump
jump
dec_
ninc
free_
jump
update mode
Normal mode (no line skip/insert capability)
0
0
0 ITU-R (CCIR): 313/312 or 263/262
non-interlaced: 312/312 or 262/262
Manual mode for line insert (“dec_ninc”=0) or skip
(“dec_ninc”=1) capability.
(*)
0
x
1
Both fields of all the frames following the writing of this value
are modified according to “lref” and “ltar” bits of registers 21-
22-23 (by default, “lref”=0 and “ltar”=1 which leads to normal
mode above).
30/65
|
|
Share Link: 