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S93VP662SI-ATE7 View Datasheet(PDF) - Summit Microelectronics

Part Name
Description
View to exact match
S93VP662SI-ATE7
Summit-Microelectronics
Summit Microelectronics Summit-Microelectronics
S93VP662SI-ATE7 Datasheet PDF : 12 Pages
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S93VP662/S93VP663
PIN CAPACITANCE
Symbol
COUT(1)
CIN(1)
Test
OUTPUT CAPACITANCE (DO)
INPUT CAPACITANCE (CS, SK, DI, ORG)
Max.
5
5
Units
pF
pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Conditions
VOUT=OV
VIN=OV
2019 PGM T4 1.0
A.C. CHARACTERISTICS
SYMBOL PARAMETER
Limits
VCC=2.7V-4.5V VCC=4.5V-5.5V
Test
Min. Max. Min. Max. UNITS Conditions
tCSS
CS Setup Time
100
50
ns
tCSH
CS Hold Time
0
0
ns VIL = 0.45V
tDIS
DI Setup Time
200
100
ns VIH = 2.4V
tDIH
DI Hold Time
200
100
ns CL = 100pF
tPD1
Output Delay to 1
0.5
0.25 µs VOL = 0.8V
tPD0
tHZ(1)
Output Delay to 0
Output Delay to High-Z
0.5
0.25 µs VOH = 2.0v
200
100
ns
CL = 100pF
tEW
Program/Erase Pulse Width
10
10 ms
tCSMIN
Minimum CS Low Time
0.5
0.25
µs
tSKHI
Minimum SK High Time
0.5
0.25
µs
tSKLOW Minimum SK Low Time
0.5
0.25
µs
tSV
Output Delay to Status Valid
0.5
0.25 µs CL = 100pF
SKMAX Maximum Clock Frequency
DC 500 DC
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
1000
KHZ
2019 PGM T6 1.0
2019 1.1 5/15/98
8
 

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