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S93VP663P-2.7TE13 View Datasheet(PDF) - Summit Microelectronics

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S93VP663P-2.7TE13
Summit-Microelectronics
Summit Microelectronics Summit-Microelectronics
S93VP663P-2.7TE13 Datasheet PDF : 12 Pages
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S93VP662/S93VP663
Erase/Write Enable and Disable
The S93VP662/VP663 powers up in the write disable
state. Any writing after power-up or after an EWDS
(write disable) instruction must first be preceded by the
EWEN (write enable) instruction. Once the write in-
struction is enabled, it will remain enabled until power to
the device is removed, or the EWDS instruction is sent.
The EWDS instruction can be used to disable all
S93VP662/VP663 write and clear instructions, and will
prevent any accidental writing or clearing of the device.
Data can be read normally from the device regardless
of the write enable/disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip
Select) pin must be deselected for a minimum of 250ns
(tCSMIN). The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the S93VP662/VP663 can be determined by
selecting the device and polling the DO pin. Once
cleared, the contents of all memory bits return to a
logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
250ns (tCSMIN). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The ready/
busy status of the S93VP662/VP663 can be determined
by selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
SK
CS
AN AN-1
DI
101
A0 DN
D0
tCS
STATUS
VERIFY
STANDBY
tSV
BUSY
tHZ
HIGH-Z
DO
READY
HIGH-Z
tEW
2019 ILL 5 1.0
Figure 3. Write Instruction Timing
SK
CS
DI
DO
2019 1.1 5/15/98
111
AN AN-1
A0
STATUS VERIFY
tCS
STANDBY
HIGH-Z
tSV
BUSY READY
tEW
Figure 4. Erase Instruction Timing
tHZ
HIGH-Z
2019 ILL6 1.0
4
 

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