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S93VP662P-ATE13 View Datasheet(PDF) - Summit Microelectronics

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S93VP662P-ATE13
Summit-Microelectronics
Summit Microelectronics Summit-Microelectronics
S93VP662P-ATE13 Datasheet PDF : 12 Pages
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S93VP662/S93VP663
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state
on the falling edge of the clock (SK). Placing the DO pin
into the high impedance state is recommended in appli-
cations where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
The format for all instructions is: one start bit; two op
code bits and either eight (x16) or nine (x8) address/
instruction bits.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the S93VP662/
VP663 will come out of the high impedance state and,
will first output an initial dummy zero bit, then begin
shifting out the data addressed (MSB first). The output
data bits will toggle on the rising edge of the SK clock
and are stable after the specified time delay (tPD0 or
tPD1).
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of 250ns (tCSMIN). The falling edge of CS will
start automatic erase and write cycle to the memory
location specified in the instruction. The ready/busy
status of the S93VP662/VP663 can be determined by
selecting the device and polling the DO pin.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deslected for a minimum
of 250ns (tCSMIN). The falling edge of CS will start the
auto erase cycle of the selected memory location. The
ready/busy status of the S93VP662/VP663 can be
determined by selecting the device and polling the DO
pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
tSKHI
t SKLOW
t CSH
SK
t DIS
DI
VALID
tCSS
CS
VALID
tDIH
t DIS
tPD0,t PD1
tCSMIN
DO
DATA V ALID
Figure 1. Sychronous Data Timing
2019 ILL 3 1.0
SK
CS
AN AN–1
A0
DI
11
0
tCS
STANDBY
HIGH-Z
tPD0
DO
0
tHZ
HIGH-Z
DN DN–1
D1 D0
Figure 2. Read Instruction Timing
2019 ILL4 1.0
2019 1.1 5/15/98
3
 

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