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AD9117 View Datasheet(PDF) - Analog Devices

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AD9117 Datasheet PDF : 52 Pages
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Data Sheet
AD9114/AD9115/AD9116/AD9117
5. Check if the self-calibration has completed by reading
Bit 6 (CALSTATI) and Bit 7 (CALSTATQ) in Register 0x0F.
Logic 1 indicates that the calibration has completed.
6. When the self-calibration has completed, write 0x00 to
Register 0x12.
7. Disable the calibration clock by clearing Bit 3 (CALCLK)
in Register 0x0E.
The AD9114/AD9115/AD9116/AD9117 allow reading and
writing of the calibration coefficients. There are 32 coefficients
in total. The read/write feature of the coefficients can be useful for
improving the results of the self-calibration routine by averaging
the results of several self-calibration cycles and loading the
averaged results back into the device.
To read the calibration coefficients, use the following steps:
1. Select which DAC core to read by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the
Q DAC in Register 0x0E. Write the address of the first
coefficient (0x01) to Register 0x10.
2. Set Bit 2 (SMEMRD) in Register 0x12 by writing 0x04 to
Register 0x12.
3. Read the 6-bit value of the first coefficient by reading the
contents of Register 0x11.
4. Clear the SMEMRD bit by writing 0x00 to Register 0x12.
5. Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by 1 for each read.
6. Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E.
To write the calibration coefficients to the device, use the
following steps:
1. Select which DAC core to write to by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the
Q DAC in Register 0x0E.
2. Set Bit 3 (SMEMWR) in Register 0x12 by writing 0x08 to
Register 0x12.
3. Write the address of the first coefficient (0x01) to
Register 0x10.
4. Write the value of the first coefficient to Register 0x11.
5. Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by one for each write.
6. Clear the SMEMWR bit by writing 0x00 to Register 0x12.
7. Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E.
COARSE GAIN ADJUSTMENT
Option 1
A coarse full-scale output current adjustment can be achieved
using the lower six bits in Register 0x0D. This adds or subtracts
up to 20% from the band gap voltage on Pin 34 (REFIO), and
the voltage on the FSADJx resistors tracks this change. As a result,
the DAC full-scale current varies by the same amount. A secondary
effect to changing the REFIO voltage is that the full-scale voltage in
the AUXDAC also changes by the same magnitude. The register
uses twos complement format, in which 011111 maximizes the
voltage on the REFIO node and 100000 minimizes the voltage.
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0
8
16
24
32
40
48
56
CODE
Figure 97. Typical VREF Voltage vs. Code
Option 2
While using the internal FSADJx resistors, each main DAC can
achieve independently controlled coarse gain using the lower six
bits of Register 0x04 (IRSET[5:0]) and Register 0x07 (QRSET[5:0]).
Unlike Coarse Gain Option 1, this impacts only the main DAC
full-scale output current. The register uses twos complement
format and allows the output current to be changed in
approximately 0.25 dB steps.
22
20
18
16
VOUT_Q OR VOUT_I
14
12
10
8
6
4
2
0
10
20
30
40
50
60
xRSET CODE
Figure 98. Effect of xRSET Code
Option 3
Even when the device is in pin mode, full-scale values can be
adjusted by sourcing or sinking current from the FSADJx pins.
Any noise injected here appears as amplitude modulation of the
output. Thus, a portion of the required series resistance (at least
20 kΩ) must be installed right at the pin. A range of ±10% is
quite practical using this method.
Option 4
As in Option 3, when the device is in pin mode, both full-scale
values can be adjusted by sourcing or sinking current from the
Rev. D | Page 45 of 52
 

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