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AD9116BCPZ View Datasheet(PDF) - Analog Devices

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Description
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AD9116BCPZ Datasheet PDF : 52 Pages
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Data Sheet
AD9114/AD9115/AD9116/AD9117
Register
Memory R/W
CLKMODE
Version
Address Bit Name
Description
0x12
7 CALRSTQ
0 (default): no action.
1: clears CALSTATQ.
6 CALRSTI
0 (default): no action.
1: clears CALSTATI.
4 CALEN
0 (default): no action.
1: initiates device self-calibration.
3 SMEMWR
0 (default): no action.
1: writes to static memory (calibration coefficients).
2 SMEMRD
0 (default): no action.
1: reads from static memory (calibration coefficients).
1 UNCALQ
0 (default): no action.
1: resets Q DAC calibration coefficients to default (uncalibrated).
0 UNCALI
0 (default): no action.
1: resets I DAC calibration coefficients to default (uncalibrated).
0x14
7:6 CLKMODEQ[1:0] Depending on CLKMODEN bit setting, these two bits reflect the phase relationship
between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retime.
If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
4 Searching
Datapath retimer status bit.
0 (default): clock relationship established.
1: indicates that the internal datapath retimer is searching for clock relationship
(device output is not usable while this bit is high).
3 Reacquire
Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship.
2 CLKMODEN
0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and read
back in CLKMODEI[1:0] and CLKMODEQ[1:0].
1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers.
1:0 CLKMODEI[1:0] Depending on CLKMODEN bit setting, these two bits reflect the phase relationship
between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
0x1F
7:0 Version[7:0]
Hardware version of the device. This register is set to 0x0A for the latest version of
the device.
Rev. D | Page 39 of 52
 

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