NXP Semiconductors
5. Pinning information
5.1 Pinning
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
A3 7
IP0 8
WRN 9
RDN 10
RxDB 11
I/M 12
TxDB 13
OP1 14
OP3 15
OP5 16
OP7 17
SC28L92A1A
(80xxx mode)
Fig 3. Pin configuration for PLCC44; 80xxx mode
39 CEN
38 RESET
37 X2
36 X1/CLK
35 RxDA
34 n.c.
33 TxDA
32 OP0
31 OP2
30 OP4
29 OP6
002aad412
A3 7
IP0 8
R/WN 9
DACKN 10
RxDB 11
I/M 12
TxDB 13
OP1 14
OP3 15
OP5 16
OP7 17
SC28L92A1A
(68xxx mode)
Fig 4. Pin configuration for PLCC44; 68xxx mode
39 CEN
38 RESETN
37 X2
36 X1/CLK
35 RxDA
34 n.c.
33 TxDA
32 OP0
31 OP2
30 OP4
29 OP6
002aad413
SC28L92_7
Product data sheet
Rev. 07 — 19 December 2007
© NXP B.V. 2007. All rights reserved.
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