SC28L92 View Datasheet(PDF) - NXP Semiconductors.
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SC28L92 Datasheet PDF : 73 Pages
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
SC28L92_7
Product data sheet
Table 31. DUART mode description
Mode
Description
Normal The transmitter and receiver operating independently.
Automatic Places the channel in the automatic echo mode, which automatically retransmits the
echo
received data. The following conditions are true while in automatic echo mode:
1. Received data is reclocked and retransmitted on the TxDA output
2. The receive clock is used for the transmitter
3. The receiver must be enabled, but the transmitter need not be enabled
4. The channel A TxRDY and TxEMT status bits are inactive
5. The received parity is checked, but is not regenerated for transmission, i.e.
transmitted parity bit is as received
6. Character framing is checked, but the stop bits are retransmitted as received
7. A received break is echoed as received until the next valid start bit is detected
8. CPU to receiver communication continues normally, but the CPU to transmitter
link is disabled
Local
Selects local loopback diagnostic mode. In this mode:
loopback 1. The transmitter output is internally connected to the receiver input
2. The transmit clock is used for the receiver
3. The TxDA output is held HIGH
4. The RxDA input is ignored
5. The transmitter must be enabled, but the receiver need not be enabled
6. CPU to transmitter and receiver communications continue normally
Remote Selects remote loopback diagnostic mode. In this mode:
loopback 1. Received data is reclocked and retransmitted on the TxDA output
2. The receive clock is used for the transmitter
3. Received data is not sent to the local CPU, and the error status conditions are
inactive
4. The received parity is not checked and is not regenerated for transmission, i.e.,
transmitted parity is as received
5. The receiver must be enabled
6. Character framing is not checked, and the stop bits are retransmitted as received
7. A received break is echoed as received until the next valid start bit is detected
Table 32. Stop bit length
MR2A[3:0] (hexadecimal)
0
1
2
3
4
5
6
7
8
9
A
Stop bit length[1]
0.563
0.625
0.688
0.750
0.813
0.875
0.938
1.000
1.563
1.653
1.688
Rev. 07 — 19 December 2007
© NXP B.V. 2007. All rights reserved.
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