A8902 View Datasheet(PDF) - Allegro MicroSystems
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A8902 Datasheet PDF : 12 Pages
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8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Current Control. The A8902CLBA provides linear current control
via the FILTER terminal, an analog voltage input. Maximum current
limit is also provided, and is controlled in four steps via the serial port.
Output current is sensed via an internal sense resistor (RS). The
voltage across the sense resistor is compared to one-tenth the voltage
at the FILTER terminal less the filter threshold voltage, or to the maxi-
mum current limit reference, whichever is lower. This transcon-
ductance function is IOUT = (VFILTER -VFILTERTH) / 10RS, where RS is
nominally 0.2 Ω and VFILTERTH is approximately 1.85 V.
POWER UP
YANK
SQ
ERROR FAST
R
FROM FLL
V DD
SPEED-CONTROL
INITIALIZATION
ERROR SLOW
V DD
FROM FLL
Ic
FILTER
C F1
Id
x1
RF1
C F2
1.85 V
CHARGE
PUMP
ERROR FAST
FROM FLL
SEQUENTIAL
LOGIC
C RES
BOOST
CHARGE
PUMP
MUX
÷10
V BB
OUT
–
+
FROM
SERIAL PORT
REGISTER
D3 AND D4
MAX CURRENT LIMIT
LINEAR
RS
CURRENT CONTROL
Dwg. EP-046
Speed Control. The A8902CLBA includes a frequency-locked
loop speed control system. This system monitors motor speed via
internal or external digital tachometer signals, generates a precision
speed reference, determines the digital speed error, and corrects the
motor current via an internal charge pump and external filtering compo-
nents on the FILTER terminal.
A once per revolution TACH signal can be generated by counting
cycles of FCOM (the number of motor poles must be selected via the
serial port). TACH is then a jitter-free signal that toggles once per
motor revolution. The rising edge of TACH triggers REF, a precision
speed reference derived by a programmable counter. The duration of
REF is set by programming the counter to count the desired number of
OSC cycles
FCOM
SECTOR
COUNT
(3 x MOTOR POLES)
D20 &
D21
ONCE-AROUND
PULSE
MUX
D19
OSC
SERIAL PORT
REGISTER
D5–D18
4-BIT
FIXED
COUNTER
14-BIT
PROGRAMMABLE
COUNTER
REF
÷2
TACH
REF
TACH
ERROR
SLOW
REF
TACH
ERROR
FAST
Dwg. EP-045
desired
total count
=
60 x fOSC
desired motor speed (rpm)
where the total count (number of oscillator
cycles) is equal to the sum of the selected
(programmed low) count numbers corre-
sponding to bits D5 through D18.
The speed error is detected as the
difference in falling edges of TACH and
REF. The speed error signals control the
error-correcting charge pump on the FILTER
terminal, which drive the external loop com-
pensation components to correct the motor
current.
Sector Mode. An external tachometer
signal, such as sector or index pulses, may
be used to create the TACH signal, rather
than the internally derived once around. To
use this mode, the signal is input to the
SECTOR terminal, and the sector mode must
be enabled via the serial port. When Switch-
ing from the once-around mode to sector
mode, it is important to monitor the SYNC
signal on DATA OUT, and switch modes only
when SYNC is low. This ensures making the
transition without disturbing the speed control
loop. The speed reference counter should be
reprogrammed at the same time.
Speed Loop Initialization (YANK). To
improve the acquire time of the speed control
loop, there is an automatic feature controlled
by an internal YANK signal. The motor is
started at the maximized programmed current
by bypassing the FILTER terminal. The
FILTER terminal is clamped to an internal
reference (the filter threshold voltage),
initializing it near the closed loop operating
point. YANK is enabled at startup and stays
high until the desired speed is reached. Once
the first error-fast occurs, indicating the motor
crossed through the desired speed, YANK
goes low. This releases the clamp on the
FILTER terminal and current control is
returned to FILTER. This feature optimizes
speed acquire and minimizes settling. The
Current Control Block Diagram illustrates the
YANK signal and its effects.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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