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FM1608-120-PG View Datasheet(PDF) - Ramtron International Corporation

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FM1608-120-PG
RAMTRON
Ramtron International Corporation RAMTRON
FM1608-120-PG Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
FRAM Design Considerations
When designing with FRAM for the first time, users
of SRAM will recognize a few minor differences.
First, bytewide FRAM memories latch each address
on the falling edge of chip enable. This allows the
address bus to change after starting the memory
access. Since every access latches the memory
address on the falling edge of /CE, users cannot
ground it as they might with SRAM.
Users who are modifying existing designs to use
FRAM should examine the memory controller for
timing compatibility of address and control pins.
Each memory access must be qualified with a low
transition of /CE. In many cases, this is the only
change required. An example of the signal
relationships is shown in Figure 2 below. Also shown
is a common SRAM signal relationship that will not
work for the FM1608.
FM1608
The reason for /CE to strobe for each address is two-
fold: it latches the new address and creates the
necessary precharge period while /CE is high.
A second design consideration relates to the level of
VDD during operation. Battery-backed SRAMs are
designed to monitor VDD in order to switch to battery
backup. They typically block user access below a
certain VDD level in order to minimize battery drain
from an otherwise active SRAM. The user can be
abruptly cut off from access to the memory in a
power down situation without warning. FRAM
memories do not need this system overhead. The
memory will not block access at any VDD level. The
user, however, should prevent the processor from
accessing memory when VDD is out-of-tolerance.
Check the min/max VDD specifications on FRAM
datasheet. The common design practice of holding a
processor in reset when VDD drops is sufficient. No
special provisions must be taken for FRAM design.
Figure 2. Memory Address and /CE Relationships
Rev. 3.0
Nov. 2004
5 of 11
 

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