LH521028A
CMOS 64K × 18 Static RAM
TIMING DIAGRAMS – WRITE CYCLE (cont’d)
Write Cycle No. 3 (Latched W Controlled Write)
Chip is selected: E, G, and SH / SL are LOW.
Write Cycle No. 4 (E Controlled)
G is LOW. DQ lines may transition to Low-Z if the falling
edge of W occurs after the falling edges of E and SH/SL.
ALE
tLHM
tASL
tWC
tAHL
ADDRESS
W
DQ
VALID ADDRESS
tAW
tAS
tWP
tLHW
tWHZ
PREVIOUS OUTPUT
tWLZ
tDW
tDH
VALID DATA
Figure 10. Write Cycle No. 3
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ALE
ADDRESS
E, SH / SL
W
DQ
tWC
tLHM
tASL
tAHL
VALID ADDRESS
tEW
tAS
tWP
tLHW
tELZ
tSLZ
tWHZ
tDW
tDH
VALID DATA
Figure 11. Write Cycle No. 4
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