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LH521028A View Datasheet(PDF) - Sharp Electronics

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Description
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LH521028A
Sharp
Sharp Electronics Sharp
LH521028A Datasheet PDF : 15 Pages
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CMOS 64K × 18 Static RAM
TIMING DIAGRAMS – WRITE CYCLE
Addresses must be stable during unlatched Write
cycles. The outputs will remain in the High-Z state if W is
LOW when E and SH / SL go LOW. If G is HIGH, the
outputs will remain in the High-Z state. Although these
examples illustrate timing with G active, it is recom-
mended that G be held HIGH for all Write cycles. This will
prevent the LH521028’s outputs from becoming active,
preventing bus contention, thereby reducing system
noise.
LH521028A
Write Cycle No. 1 (Unlatched W Controlled Write)
Chip is selected: E, G, and SH / SL are LOW, ALE is
High. Using only W to control Write cycles may not offer
the best performance since both tWHZ and tDW timing
specifications must be met.
Write Cycle No. 2 (E, SL, SH Controlled Write)
G is LOW. DQ lines may transition to Low-Z if the falling
edge of W occurs after the falling edge of E, SH/SL if G is
LOW.
ADDRESS
W
DQ
ADDRESS
E, SL, SH
W
DQ
tWC
VALID ADDRESS
tAW
tAH
tAS
tWP
tWHZ
PREVIOUS OUTPUT
tDW
VALID DATA
tWLZ
tDH
Figure 8. Write Cycle No. 1
tWC
VALID ADDRESS
tEW
tAS
tWP
tAH
tELZ
tWHZ
tDW
tDH
VALID DATA
Figure 9. Write Cycle No. 2
521028-6
521028-7
11
 

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