Accelerator Series FPGAs – ACT™ 3 Family
A1440A, A14V40A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
I/O Module – TTL Output Timing1
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
tDHS
tDLS
tENZHS
Data to Pad, High Slew
Data to Pad, Low Slew
Enable to Pad, Z to H/L,
Hi Slew
tENZLS
Enable to Pad, Z to H/L,
Lo Slew
tENHSZ
Enable to Pad, H/L to Z,
Hi Slew
tENLSZ
Enable to Pad, H/L to Z,
Lo Slew
tCKHS
IOCLK Pad to Pad H/L,
Hi Slew
tCKLS
IOCLK Pad to Pad H/L,
Lo Slew
dTLHHS
Delta Low to High, Hi Slew
dTLHLS
Delta Low to High, Lo Slew
dTHLHS
Delta High to Low, Hi Slew
dTHLLS
Delta High to Low, Lo Slew
I/O Module – CMOS Output Timing1
5.0
5.6
6.4
7.5
9.8 ns
8.0
9.0
10.2
12.0
15.6 ns
4.0
4.5
5.1
6.0
7.8 ns
7.4
8.3
9.4
11.0
14.3 ns
7.4
8.3
9.4
11.0
14.3 ns
7.4
8.3
9.4
11.0
14.3 ns
8.5
8.5
9.5
11.0
14.3 ns
11.3
11.3
13.5
15.0
19.5 ns
0.02
0.02
0.03
0.03
0.04 ns/pF
0.05
0.05
0.06
0.07
0.09 ns/pF
0.04
0.04
0.04
0.05
0.07 ns/pF
0.05
0.05
0.06
0.07
0.09 ns/pF
tDHS
tDLS
tENZHS
Data to Pad, High Slew
Data to Pad, Low Slew
Enable to Pad, Z to H/L,
Hi Slew
tENZLS
Enable to Pad, Z to H/L,
Lo Slew
tENHSZ
Enable to Pad, H/L to Z,
Hi Slew
tENLSZ
Enable to Pad, H/L to Z,
Lo Slew
tCKHS
IOCLK Pad to Pad H/L,
Hi Slew
tCKLS
IOCLK Pad to Pad H/L,
Lo Slew
dTLHHS
Delta Low to High, Hi Slew
dTLHLS
Delta Low to High, Lo Slew
dTHLHS
Delta High to Low, Hi Slew
dTHLLS
Delta High to Low, Lo Slew
Note:
1. Delays based on 35pF loading.
6.2
7.0
7.9
9.3
12.1 ns
11.7
13.1
14.9
17.5
22.8 ns
5.2
5.9
6.6
7.8
10.1 ns
8.9
10.0
11.3
13.3
17.3 ns
7.4
8.3
9.4
11.0
14.3 ns
7.4
8.3
9.4
11.0
14.3 ns
9.0
9.0
10.1
11.8
14.3 ns
13.0
13.0
15.6
17.3
22.5 ns
0.04
0.04
0.05
0.06
0.08 ns/pF
0.07
0.08
0.09
0.11
0.14 ns/pF
0.03
0.03
0.03
0.04
0.05 ns/pF
0.04
0.04
0.04
0.05
0.07 ns/pF
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