Accelerator Series FPGAs – ACT 3 Family
A1460A, A14V60A Timing Characteristics (continued)
Table 2-31 • A1460A, A14V60A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
I/O Module Input Propagation Delays
–3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units
Parameter/Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tINY Input Data Pad to Y
tICKY Input Reg IOCLK Pad to Y
tOCKY Output Reg IOCLK Pad to Y
tICLRY Input Asynchronous Clear to Y
tOCLRY Output Asynchronous Clear to Y
Predicted Input Routing Delays2
2.8
3.2
3.6
4.2
4.7
5.3
6.0
7.0
4.7
5.3
6.0
7.0
4.7
5.3
6.0
7.0
4.7
5.3
6.0
7.0
5.5 ns
9.2 ns
9.2 ns
9.2 ns
9.2 ns
tRD1 FO = 1 Routing Delay
0.9
1.0
1.1
1.3
tRD2 FO = 2 Routing Delay
1.2
1.4
1.6
1.8
tRD3 FO = 3 Routing Delay
1.4
1.6
1.8
2.1
tRD4 FO = 4 Routing Delay
1.7
1.9
2.2
2.5
tRD8 FO = 8 Routing Delay
2.8
3.2
3.6
4.2
I/O Module Sequential Timing (wrt IOCLK pad)
1.7 ns
2.4 ns
2.8 ns
3.3 ns
5.5 ns
tINH Input F-F Data Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU Input F-F Data Setup
1.3
1.5
1.8
2.0
2.0
ns
tIDEH Input Data Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tIDESU Input Data Enable Setup
5.8
6.5
7.5
8.6
8.6
ns
tOUTH Output F-F Data hold
0.7
0.8
0.9
1.0
1.0
ns
tOUTSU Output F-F Data Setup
0.7
0.8
0.9
1.0
1.0
ns
tODEH Output Data Enable Hold
0.3
0.4
0.4
0.5
0.5
ns
fODESU Output Data Enable Setup
1.3
1.5
1.7
2.0
2.0
ns
Notes:
5. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.
6. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
Revision 3
2- 35