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SC1186 View Datasheet(PDF) - Semtech Corporation

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SC1186 Datasheet PDF : 15 Pages
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SC1186
POWER MANAGEMENT
Component Selection (Cont.)
To a first order approximation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
Using 1.5X Room temp RDS(ON) to allow for temperature rise.
FET type
IRL34025
IRL2203
Si4410
RDS(on) (m)
15
10.5
20
PD (W)
1.69
1.19
2.26
Package
D2Pak
D2Pak
S0-8
BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into conduc-
tion at the beginning and end of the bottom switch con-
duction period, so when the FET turns on and off, there
is very little voltage across it, resulting in low switching
losses. Conduction losses for the FET can be determined
by:
PCOND = IO2 RDS(on) (1− δ)
For the example above:
FET type
IRL34025
IRL2203
Si4410
RDS(on) (m)
15
10.5
20
PD (W)
1.33
0.93
1.77
Package
D2Pak
D2Pak
S0-8
Each of the package types has a characteristic thermal
impedance. For the surface mount packages on double
sided FR4, 2 oz printed circuit board material, thermal
impedances of 40oC/W for the D2PAK and 80oC/W for the
SO-8 are readily achievable. The corresponding tempera-
ture rise is detailed below:
FET type
IRL34025
IRL2203
Si4410
Temperature Rise (OC)
Top FET
Bottom FET
67.6
53.2
47.6
37.2
180.8
141.6
INPUT CAPACITORS - since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restric-
tions on input di/dt. These restrictions require useable
energy storage within the converter circuitry, either as
extra output capacitance or, more usually, additional in-
put capacitors. Choosing low ESR input capacitors will
help maximize ripple rating for a given size.
GATE RESISTOR SELECTION - The gate resistors for the
top and bottom switching FETs limit the peak gate current
and hence control the transition time. It is important to
control the off time transition of the top FET, it should be
fast to limit switching losses, but not so fast as to cause
excessive phase node oscillation below ground as this can
lead to current injection in the IC substrate and erratic
behaviour or latchup. The actual value should be deter-
mined in the application, with the final layout and FETs.
SHORT CIRCUIT PROTECTION - LINEARS
The Short circuit feature on the linear controllers is imple-
mented by using the Rds(on) of the FETs. As output cur-
rent increases, the regulation loop maintains the output
voltage by turning the FET on more and more. Eventually,
as the Rds(on) limit is reached, the FET will be unably to
turn on more fully, and output voltage will start to fall.
When the output voltage falls to approximately 40% of
nominal, the LDO controller is latched off, setting output
voltage to 0. Power must be cycled to reset the latch.
To prevent false latching due to capacitor inrush currents
or low supply rails, the current limit latch is initially dis-
abled. It is enabled at a preset time (nominally 2ms) after
both the LDOV and LDOEN pins rise above their lockout
points.
To be most effective, the linear FET Rds(on) should not be
selected artificially low, the FET should be chosen so that,
at maximum required current, it is almost fully turned on.
If, for example, a linear supply of 1.5V at 4A is required
from a 3.3V ± 5% rail, max allowable Rds(on) would be.
Rds(on)max = (0.95*3.3-1.5)/4 » 400m
To allow for temperature effects 200mwould be a suit-
able room temperature maximum, allowing a peak short
circuit current of approximately 15A for a short time be-
fore shutdown.
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
position, power dissipation will be approximately halved
and temperature rise reduced by a factor of 4.
2004 Semtech Corp.
10
www.semtech.com
 

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