UT62L1024I View Datasheet(PDF) - Utron Technology Inc

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Description

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UT62L1024I

No description available.

Utron Technology Inc 



Rev. 1.1

UTRON

WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6)

Address

CE

CE2

tAS

WE

Dout

Din

UT62L1024(I)

128K X 8 BIT LOW POWER CMOS SRAM

tWC

tAW

tCW

tWP

tWHZ

(4)

tWR

High-Z

tOW

(4)

tDW

tDH

Data Valid

WRITE CYCLE 2 ( CE and CE2 Controlled) (1,2,5,6)

tWC

Address

CE

tAS

tAW

tCW

CE2

tWP

WE

tWHZ

Dout

(4)

Din

tWR

High-Z

tDW

tDH

Data Valid

Notes :

1. WE , CE must be high or CE2 must be low during all address transitions.

2.A write occurs during the overlap of a low CE , high CE2, low WE .

3.During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a

high impedance state.

6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

7

P80078

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