ADP2384 View Datasheet(PDF) - Analog Devices

Part Name

Description

View to exact match

ADP2384

20 V, 4 A, Synchronous, Step-Down DC-to-DC Regulator

Analog Devices 

Data Sheet

SOFT START

The ADP2384 has integrated soft start circuitry to limit the output

voltage rising time and reduce inrush current at startup. The

internal soft start time is calculated using the following equation:

tSS_INT = 1600 (ms)

fSW (kHz)

A slower soft start time can be programmed by using the SS pin.

When a capacitor is connected between the SS pin and GND, an

internal current charges the capacitor to establish the soft start

ramp. The soft start time is calculated using the following equation:

tSS_EXT = 0.6 V × CSS

ISS _UP

where:

CSS is the soft start capacitance.

ISS_UP is the soft start pull-up current (3.2 µA).

The internal error amplifier includes three positive inputs: the

internal reference voltage, the internal digital soft start voltage,

and the SS pin voltage. The error amplifier regulates the FB

voltage to the lowest of the three voltages.

If the output voltage is charged prior to turn-on, the ADP2384

prevents reverse inductor current that would discharge the output

capacitor. This function remains active until the soft start

voltage exceeds the voltage on the FB pin.

POWER GOOD

The power-good pin (PGOOD) is an active high, open-drain

output that requires an external resistor to pull it up to a voltage.

A logic high on the PGOOD pin indicates that the voltage on

the FB pin (and, therefore, the output voltage) is within regulation.

The power-good circuitry monitors the output voltage on the FB

pin and compares it to the rising and falling thresholds that are

specified in Table 1. If the rising output voltage exceeds the target

value, the PGOOD pin is held low. The PGOOD pin continues

to be held low until the falling output voltage returns to the

target value.

If the output voltage falls below the target output voltage, the

PGOOD pin is held low. The PGOOD pin continues to be held

low until the rising output voltage returns to the target value.

The power-good rising and falling thresholds are shown in

Figure 30. There is a 1024-cycle waiting period before the PGOOD

pin is pulled from low to high, and there is a 16-cycle waiting

period before the PGOOD pin is pulled from high to low.

VOUT RISING

ADP2384

VOUT FALLING

116.7%

105%

100%

95%

90%

PGOOD

1024 CYCLE

DEGLITCH

16 CYCLE

DEGLITCH

1024 CYCLE 16 CYCLE

DEGLITCH DEGLITCH

Figure 30. PGOOD Rising and Falling Thresholds

PEAK CURRENT-LIMIT AND SHORT-CIRCUIT

PROTECTION

The ADP2384 has a peak current-limit protection circuit to

prevent current runaway. During the initial soft start, the

ADP2384 uses frequency foldback to prevent output current

runaway. The switching frequency is reduced according to the

voltage on the FB pin, which allows more time for the inductor

to discharge. The correlation between the switching frequency

and the FB pin voltage is shown in Table 5.

Table 5. FB Pin Voltage and Switching Frequency

FB Pin Voltage

Switching Frequency

VFB ≥ 0.4 V

fSW

0.4 V > VFB ≥ 0.2 V

fSW/2

VFB < 0.2 V

fSW/4

For protection against heavy loads, the ADP2384 uses a hiccup

mode for overcurrent protection. When the inductor peak current

reaches the current-limit value, the high-side MOSFET turns off

and the low-side MOSFET turns on until the next cycle. The over-

current counter increments during this process. If the overcurrent

counter reaches 10 or the FB pin voltage falls to 0.4 V after the

soft start, the regulator enters hiccup mode. The high-side and

low-side MOSFETs are both turned off. The regulator remains

in hiccup mode for 4096 clock cycles and then attempts to restart.

If the current-limit fault has cleared, the regulator resumes normal

operation. Otherwise, it reenters hiccup mode.

The ADP2384 also provides a sink current limit to prevent the

low-side MOSFET from sinking a lot of current from the load.

When the voltage across the low-side MOSFET exceeds the sink

current-limit threshold, which is typically 20 mV, the low-side

MOSFET turns off immediately for the rest of the cycle. Both high-

side and low-side MOSFETs turn off until the next clock cycle.

In some cases, the input voltage (VPVIN) ramp rate is too slow or

the output capacitor is too large for the output to reach regulation

during the soft start process, which causes the regulator to enter

the hiccup mode. To avoid such occurrences, use a resistor

divider at the EN pin to program the input voltage UVLO,

or use a longer soft start time.

Rev. A | Page 13 of 24

Share Link: