GS82564Z18GB-400 View Datasheet(PDF) - Giga Semiconductor

Part Name

Description

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GS82564Z18GB-400

288Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

GS82564Z18/36(GB/GD)

119- & 165-Bump BGA

Commercial Temp

Industrial Temp

288Mb Pipelined and Flow Through

Synchronous NBT SRAM

400 MHz–200 MHz

2.5 V or 3.3 V VDD

2.5 V or 3.3 V I/O

Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb

devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• RoHS-compliant 119- and 165-bump BGA packages

Functional Description

The GS82564Z18/36 is a 288Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS82564Z18/36 may be configured by the user to operate

in Pipeline or Flow Through mode. Operating as a pipelined

synchronous device, in addition to the rising-edge-triggered

registers that capture input signals, the device incorporates a

rising edge triggered output register. For read cycles, pipelined

SRAM output data is temporarily stored by the edge-triggered

output register during the access cycle and then released to the

output drivers at the next rising edge of clock.

The GS82564Z18/362 is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 119-bump or 165-bump BGA package.

Parameter Synopsis

Pipeline

3-1-1-1

Flow Through

2-1-1-1

tKQ

tCycle

Curr (x18)

Curr (x36)

tKQ

tCycle

Curr (x18)

Curr (x36)

-400 -333 -250 -200 Unit

2.5

2.5

2.5

3.0

ns

2.5

3.0

4.0

5.0

ns

730 650 540 520 mA

820 720 590 470 mA

4.0

4.5

5.5

6.5

ns

4.0

4.5

5.5

6.5

ns

520 500 440 410 mA

540 550 500 470 mA

Rev: 1.02 5/2017

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2015, GSI Technology

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