AD7871 View Datasheet(PDF) - Analog Devices
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AD7871 Datasheet PDF : 24 Pages
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AD7871/AD7872
Serial Interfacing
Both the AD7871 and the AD7872 have an identical serial
interface. The diagrams that follow show the AD7872 interfaces
only, but the AD7871 could just as easily be used in these
circuits. Figure 24, Figure 25, and Figure 26 show the AD7872
connected to three popular DSPs. In all three interfaces,
CONVST is used to start the conversion because this does not
activate the parallel bus. Thus, the microprocessor can continue
to use its parallel bus regardless of the state of the AD7872. The
interfaces show a timer driving the CONVST input but this
could be generated from a decoded address if required.
AD7872 to DSP Type 1 Serial Interface
Figure 24 shows a serial interface between the AD7872 and DSP
Type 1. The interface arrangement is two-wire with the AD7872
configured for noncontinuous clock operation CONTROL =
0 V). DSP Type 1 is configured for normal mode asynchronous
operation with gated clock. It is set up for a 16-bit word with
SCK as an input and the FSL control bit set to a 0. In this
configuration, the DSP Type 1 assumes valid data on the first
falling edge of SCK. Because the AD7872 provides valid data on
this first edge, there is no need for a strobe or framing pulse for
the data. SCLK and SDATA are three-stated when the AD7872
is not performing a conversion. During conversion, data is valid
on the SDATA output of the AD7872 and is clocked into the
Receive Data Shift Register of DSP Type 1. When this register
has received 16 bits of data, it generates an internal interrupt on
DSP Type 1 to read the data from the register.
TIMER
5V
DSP
TYPE 1
4.7kΩ
2kΩ
SCK
SRD
AD7872*
CONVST
CONTROL
SCLK
SDATA
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 24. AD7872 to DSP Type 1 Interface
DSP Type 1 and AD7872 can also be configured for continuous
clock operation. In this case a strobe pulse is required by DSP
Type 1 to indicate when data is valid. The SSTRB output of the
AD7872 is inverted and applied to the SC1 input of DSP
Type 1 to provide this strobe pulse. All other conditions and
connections are the same as for the gated clock operation.
Data Sheet
AD7872 to DSP Type 2 Serial Interface
Figure 25 shows a serial interface between the AD7872 and DSP
Type 2. The AD7872 is configured for continuous clock
operation. Note that the ADC will not interface correctly to a
DSP if it is configured for a noncontinuous clock. Data is
clocked into the data receive register (DRR) of a DSP during
conversion. As with the previous interfaces, when a 16-bit word
is received by the DSP it generates an internal interrupt to read
the data from the DRR.
DSP
TYPE 2
FSR
CLKR
DR
+5V
4.7kΩ 2kΩ
TIMER
–5V
4.7kΩ
AD7872*
CONVST
CONTROL
SSTRB
SCLK
SDATA
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 25. AD7872 to DSP Type 2 Interface
AD7872 to a DSP Microcomputer Serial Interface
Figure 26 shows a serial interface between the AD7872 and a
DSP microcomputer. The AD7872 is configured for continuous
clock operation. Data is clocked into the serial port register of
the microcomputer during conversion. As with the previous
interfaces, when a 16-bit data word is received by a DSP
microcomputer an internal microprocessor interrupt is
generated and the data is read from the serial port register.
DSP
MICROCOMPUTER
FSR
SCLK
DR
+5V
4.7kΩ 2kΩ
TIMER
–5V
4.7kΩ
AD7872*
CONVST
CONTROL
SSTRB
SCLK
SDATA
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 26. AD7872 to a DSP Microcomputer Serial Interface
STANDALONE OPERATION
The AD7871 can be used in its Mode 2, parallel mode for
standalone operation. In this case, conversion is initiated with a
pulse to the CS input. This pulse must be longer than the
conversion time of the ADC. The BUSY output is used to drive
the RD input. Data is latched from the AD7871 DB0 to DB11
outputs to an external latch on the rising edge of BUSY.
Rev. E | Page 16 of 24
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